57.5.4 SFC Interrupt Disable Register

The following configuration values are valid for all listed bit names of this register:

0: No effect

1: Disables the corresponding interrupt

Name:	SFC_IDR
Offset:	0x14
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
							ACE
Access							W
Reset							–


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
				LCHECK			PGMF	PGMC
Access				W			W	W
Reset				–			–	–

Bit 17 – ACE Manufacturer Area Check Error Interrupt Disable

Bit 4 – LCHECK Live Integrity Check Error Interrupt Disable

Bit 1 – PGMF Programming Sequence Failed Interrupt Disable

Bit 0 – PGMC Programming Sequence Completed Interrupt Disable