47.10.12 USART Interrupt Disable Register (SPI_MODE)
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
This register can only be written if the WPITEN bit is cleared in the USART Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt.
| Name: | FLEX_US_IDR (SPI_MODE) |
| Offset: | 0x20C |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CMP | NSSE | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| UNRE | TXEMPTY | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVRE | TXRDY | RXRDY | |||||||
| Access | W | W | W | ||||||
| Reset | – | – | – |