15.5.17 L2CC Invalidate Physical Address Line Register

Name:	L2CC_IPALR
Offset:	0x770
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	TAG[17:10]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	TAG[9:2]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TAG[1:0]		IDX[8:3]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	IDX[2:0]							C
Access	R/W	R/W	R/W					R/W
Reset	0	0	0					0

Bits 31:14 – TAG[17:0] Tag Number

Bits 13:5 – IDX[8:0] Index Number

Bit 0 – C Cache Synchronization Status

Value	Description
0	No background operation is in progress. When written, must be zero.
1	A background operation is in progress.