47.7.8.5 Character Transmission

The characters are sent by writing in the Transmit Holding register (FLEX_US_THR). An additional condition for transmitting a character can be added when the USART is configured in SPI Host mode. In the “USART Mode register (SPI_MODE)” (FLEX_US_MR), the value configured on the WRDBT bit can prevent any character transmission (even if FLEX_US_THR has been written) while the receiver side is not ready (character not read). When WRDBT = 0, the character is transmitted whatever the receiver status. If WRDBT = 1, the transmitter waits for the Receive Holding register (FLEX_US_RHR) to be read before transmitting the character (RXRDY flag cleared), thus preventing any overflow (character loss) on the receiver side.

The chip select line is deasserted for a period equivalent to 3 bits between the transmission of two data.

The transmitter reports two status bits in FLEX_US_CSR: TXRDY (Transmitter Ready), which indicates that FLEX_US_THR is empty and TXEMPTY, which indicates that all the characters written in FLEX_US_THR have been processed. When the current character processing is completed, the last character written in FLEX_US_THR is transferred into the shift register of the transmitter and FLEX_US_THR is emptied, and thus TXRDY rises.

Both the TXRDY and the TXEMPTY bits are low when the transmitter is disabled. Writing a character in FLEX_US_THR while TXRDY is low has no effect and the written character is lost.

If the USART is in SPI Client mode and if a character must be sent while FLEX_US_THR is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is cleared by writing a one to the FLEX_US_CR.RSTSTA bit.

In SPI Host mode, the client select line (NSS) is asserted at low level one t_bit (t_bit being the nominal time required to transmit a bit) before the transmission of the MSB bit and released at high level one t_bit after the transmission of the LSB bit. So, the client select line (NSS) is always released between each character transmission and a minimum delay of three t_bit always inserted. However, in order to address client devices supporting the CSAAT mode (Chip Select Active After Transfer), the client select line (NSS) can be forced at low level by writing a one to the FLEX_US_CR.RTSEN bit. The client select line (NSS) can be released at high level only by writing a one to the FLEX_US_CR.RTSDIS bit (for example, when all data have been transferred to the client device).

In SPI Client mode, the transmitter does not require a falling edge of the client select line (NSS) to initiate a character transmission but only a low level. However, this low level must be present on the client select line (NSS) at least one t_bit before the first serial clock cycle corresponding to the MSB bit.