51.10.2.1 SDMMC Tuning Sequence

The SDMMC tuning sequence must only be done when SD/SDIO SDR104 or e.MMC HS200 is selected and for a 100-MHz SDCLK frequency or higher.

1. Enable the retuning timer (SDMMC_RTC1R.TMREN = 1).
2. Configure the retuning period by setting SDMMC_RTCVR.TCVAL.
3. Set SDMMC_RTISTER.TEVT to ‘1’ so that the TEVT status flag in SDMMC_RTISTR rises each time the retuning timer counter period elapses.
4. Set SDMMC_RTISIER.TEVT to ‘1’ to generate an interrupt on the TEVT status flag assertion (optional).
5. Execute the tuning procedure as defined in “Sampling Clock Tuning Procedure” in the “SD Host Controller Simplified Specification V3.00” .
6. Start the retuning timer count (write SDMMC_RTC2R.RLD to 1). At this step, data can be read by the SDMMC.
7. Each time SDMMC_RTISTR.TEVT is set to ‘1’:

   a. Execute the tuning procedure as defined in “Sampling Clock Tuning Procedure” in the “SD Host Controller Simplified Specification V3.00” before issuing the next command.

   b. Restart the retuning timer count (write SDMMC_RTC2R.RLD to ‘1’).

   c. Resume data reading from the device.

When several instances of SDMMC are implemented in a product, the TEVT status flag of each SDMMC instance can be checked by reading SDMMC_RTSSR.