15.5.7 L2CC Event Counter Control Register
| Name: | L2CC_ECR |
| Offset: | 0x200 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EVC1RST | EVC0RST | EVCEN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – EVC1RST Event Counter 1 Reset
| Value | Description |
|---|---|
| 0 | No effect, always read as zero. |
| 1 | Resets Counter 1. |
Bit 1 – EVC0RST Event Counter 0 Reset
| Value | Description |
|---|---|
| 0 | No effect, always read as zero. |
| 1 | Resets Counter 0. |
Bit 0 – EVCEN Event Counter Enable
| Value | Description |
|---|---|
| 0 | Disables Event Counter. This is the default value. |
| 1 | Enables Event Counter. |