50.7.13 QSPI Scrambling Mode Register
This register can only be written if bit WPEN is cleared in the QSPI Write Protection Mode Register.
| Name: | QSPI_SMR |
| Offset: | 0x40 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RVDIS | SCREN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – RVDIS Scrambling/Unscrambling Random Value Disable
| Value | Description |
|---|---|
| 0 | The scrambling/unscrambling algorithm includes the user scrambling key plus a random value that may differ between devices. |
| 1 | The scrambling/unscrambling algorithm includes only the user scrambling key. |
Bit 0 – SCREN Scrambling/Unscrambling Enable
0 (DISABLED): The scrambling/unscrambling is disabled.
1 (ENABLED): The scrambling/unscrambling is enabled.