37.10.5 Coding Timing Parameters

All timing parameters are defined for one chip select and are grouped together in one register according to their type:

  • The HSMC_SETUP register groups the definition of all setup parameters:
 NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
  • The HSMC_PULSE register groups the definition of all pulse parameters:
 NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
  • The HSMC_CYCLE register groups the definition of all cycle parameters:
 NRD_CYCLE, NWE_CYCLE

The table below shows how the timing parameters are coded and their permitted range.

Table 37-4. Coding and Range of Timing Parameters
Coded Value Number of Bits Effective Value Permitted Range
Coded Value Effective Value
setup [5:0] 6 128 x setup[5] + setup[4:0] 0 ≤ setup ≤ 31 0..31
32 ≤ setup ≤ 63 128..(128 + 31)
pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 ≤ pulse ≤ 63 0..63
64 ≤ pulse ≤ 127 256..(256 + 63)
cycle[8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 ≤ cycle ≤ 127 0..127
128 ≤ cycle ≤ 255 256..(256 + 127)
256 ≤ cycle ≤ 383 512..(512 + 127)
384 ≤ cycle ≤ 511 768..(768 + 127)