51.12.33 SDMMC Host Control 2 Register (e.MMC)
| Name: | SDMMC_HC2R (e.MMC) |
| Offset: | 0x3E |
| Reset: | 0x0000 |
| Property: | Read/Write |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PVALEN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SCLKSEL | EXTUN | DRVSEL[1:0] | HS200EN[3:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – PVALEN Preset Value Enable
As the operating SDCLK frequency and I/O driver strength depend on the system implementation, it is difficult to determine these parameters in the standard host driver. When Preset Value Enable (PVALEN) is set to 1, automatic SDCLK frequency generation and driver strength selection are performed without considering system-specific conditions. This bit enables the functions defined in SDMMC_PVR.
If this bit is set to 0, SDMMC_HC2R.DRVSEL, SDMMC_CCR.SDCLKFSEL and SDMMC_CCR.CLKGSEL are set by the user.
If this bit is set to 1, SDMMC_HC2R.DRVSEL, SDMMC_CCR.SDCLKFSEL and SDMMC_CCR.CLKGSEL are set by the SDMMC as specified in SDMMC_PVR.
| Value | Description |
|---|---|
| 0 | SDCLK and Driver strength are controlled by the user. |
| 1 | Automatic selection by Preset Value is enabled. |
Bit 7 – SCLKSEL Sampling Clock Select
The SDMMC uses this bit to select the sampling clock to receive CMD and DAT.
This bit is set by the tuning procedure and is valid after completion of tuning (when EXTUN is cleared). Setting 1 means that tuning is completed successfully and setting 0 means that tuning has failed.
Writing 1 to this bit is meaningless and ignored. A tuning circuit is reset by writing to 0. This bit can be cleared by setting EXTUN to 1. Once the tuning circuit is reset, it takes time to complete a tuning sequence. Therefore, the user should keep this bit to 1 to perform a retuning sequence to complete a retuning sequence in a short time. Changing this bit is not allowed while the SDMMC is receiving a response or a read data block. See Figure 2.29 in the “SD Host Controller Simplified Specification V3.00”.
| Value | Description |
|---|---|
| 0 |
The fixed clock is used to sample data. |
| 1 |
The tuned clock is used to sample data. |
Bit 6 – EXTUN Execute Tuning
This bit is set to 1 to start the tuning procedure and is automatically cleared when the tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select (SCLKSEL). The tuning procedure is aborted by writing 0. See Figure 2.29 in the “SD Host Controller Simplified Specification V3.00”.
| Value | Description |
|---|---|
| 0 |
Not tuned or tuning completed |
| 1 |
Execute tuning |
Bits 5:4 – DRVSEL[1:0] Driver Strength Select
The SDMMC output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective. This field can be set according to the Driver Type A, C and D support bits in SDMMC_CA1R.
This field depends on setting of Preset Value Enable (PVALEN):
– PVALEN = 0: This field is set by the user.
– PVALEN = 1: This field is automatically set by a value specified in one of the SDMMC_PVRx.
| Value | Name | Description |
|---|---|---|
| 0 | TYPEB |
Driver Type B is selected (Default) |
| 1 | TYPEA |
Driver Type A is selected |
| 2 | TYPEC |
Driver Type C is selected |
| 3 | TYPED |
Driver Type D is selected |
Bits 3:0 – HS200EN[3:0] HS200 Mode Enable
This field is used to select the e.MMC HS200 mode. When HS200EN is set to B(hexa), the HS200 mode is enabled. Any other value except 0 is forbidden when interfacing an e.MMC device.
If Preset Value Enable is set to 1, SDMMC sets SDCLK Frequency Select (SDCLKFSEL), Clock Generator Select (CLKGSEL) in SDMMC_CCR and Driver Strength Select (DRVSEL) according to SDMMC_PVR. In this case, one of the preset value registers is selected by this field. The user needs to reset SD Clock Enable (SDCLKEN) before changing this field to avoid generating a clock glitch. After setting this field, the user sets SDCLKEN to 1 again.
Note: This field is effective only if DDR in SDMMC_MC1R is set to 0.