47.7.8.3 Data Transfer

Up to nine data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.

The number of data bits is selected by the CHRL field and the MODE9 bit in FLEX_US_MR. The nine bits are selected by setting the MODE9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI mode (Host or Client).

Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the FLEX_US_MR.CPOL bit. The clock phase is programmed with the CPHA bit. These two parameters determine the edges of the clock signal upon which data are driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a host/client pair must use the same parameter pair values to communicate. If multiple clients are used and fixed in different configurations, the host must reconfigure itself each time it needs to communicate with a different client.