47.10.11 USART Interrupt Disable Register
For SPI-specific configurations, see USART Interrupt Disable Register (SPI_MODE).
For LIN-specific configurations, see USART Interrupt Disable Register (LIN_MODE).
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt.
| Name: | FLEX_US_IDR |
| Offset: | 0x20C |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MANE | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CMP | CTSIC | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NACK | ITER | TXEMPTY | TIMEOUT | ||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PARE | FRAME | OVRE | RXBRK | TXRDY | RXRDY | ||||
| Access | W | W | W | W | W | W | |||
| Reset | – | – | – | – | – | – |