34.5.9 Input Glitch and Debouncing Filters

Optional input glitch and debouncing filters are independently programmable on each I/O line.

The glitch filter can filter a glitch with a duration of less than 1/2 peripheral clock and the debouncing filter can filter a pulse of less than 1/2 period of a programmable divided slow clock.

The selection between glitch filtering or debounce filtering is done by writing the PIO_CFGR.IFSCEN. The selected filtering mode is applied to the I/O line(s) defined in PIO_MSKRx.

If IFSCEN = 0: The glitch filter can filter a glitch with a duration of less than 1/2 peripheral clock period.
If IFSCEN = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 programmable divided slow clock period.

For the debouncing filter, the period of the divided slow clock is performed by writing in the DIV field of the Secure PIO Slow Clock Divider Debouncing Register (S_PIO_SCDR): t_{div_slck} = ((DIV + 1) × 2) × t_slck.

When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock cycle (selected clock represents PIO clock or divided slow clock depending on IFSCEN configuration) is automatically rejected. A pulse of a duration equal to 1/2 clock cycle may be filtered or not depending on the clock jitter.

The filters also introduce some latencies, illustrated in the figures below .

The glitch filter of each I/O line is controlled by PIO_CFGR.IFEN. Setting PIO_CFGRx.IFEN enables the glitch filter of the I/O line(s) defined in PIO_MSKRx.

When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSRx and on the input change interrupt detection. The glitch and debouncing filters require that the PIO Controller clock is enabled.

Figure 34-5. Input Debouncing Filter Timing