49.8.1 SPI Control Register
| Name: | SPI_CR |
| Offset: | 0x00 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FIFODIS | FIFOEN | LASTXFER | |||||||
| Access | W | W | W | ||||||
| Reset | – | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RXFCLR | TXFCLR | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| REQCLR | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWRST | SPIDIS | SPIEN | |||||||
| Access | W | W | W | ||||||
| Reset | – | – | – |
Bit 31 – FIFODIS FIFO Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the Transmit and Receive FIFOs. |
Bit 30 – FIFOEN FIFO Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the Transmit and Receive FIFOs. |
Bit 24 – LASTXFER Last Transfer
Refer to section Peripheral Selection for more details.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The current NPCS is deasserted after the character written in TD has been transferred. When SPI_CSRx.CSAAT is set, the communication with the current serial peripheral can be closed by raising the corresponding NPCS line as soon as TD transfer is completed. |
Bit 17 – RXFCLR Receive FIFO Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Empties the Receive FIFO. |
Bit 16 – TXFCLR Transmit FIFO Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Empties the Transmit FIFO. |
Bit 12 – REQCLR Request to Clear the Comparison Trigger
Asynchronous partial wake-up enabled:
0: No effect.
1: Clears the potential clock request currently issued by SPI, thus the potential system wakeup is cancelled.
Asynchronous partial wake-up disabled:
0: No effect.
1: Restarts the comparison trigger to enable SPI_RDR loading.
Bit 7 – SWRST SPI Software Reset
The SPI is in Client mode after software reset.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. |
Bit 1 – SPIDIS SPI Disable
All pins are set in Input mode after completion of the transmission in progress, if any.
If a transfer is in progress when SPIDIS is set, the SPI completes the transmission of the shifter register and does not start any new transfer, even if SPI_THR is loaded.
If both SPIEN and SPIDIS are equal to one when SPI_CR is written, the SPI is disabled.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the SPI. |
Bit 0 – SPIEN SPI Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the SPI to transfer and receive data. |