56.7.49 PWM External Trigger Register

This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.

Name: PWM_ETRGx
Offset: 0x042C + (x-1)*0x20 [x=1..2]
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 RFENTRGSRCTRGFILTTRGEDGE  TRGMODE[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
 MAXCNT[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 MAXCNT[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 MAXCNT[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 31 – RFEN Recoverable Fault Enable

ValueDescription
0

The TRGINx signal does not generate a recoverable fault.

1

The TRGINx signal generate a recoverable fault in place of the fault x input.

Bit 30 – TRGSRC Trigger Source

ValueDescription
0

The TRGINx signal is driven by the PWMEXTRGx input.

1

The TRGINx signal is driven by the Analog Comparator Controller.

Bit 29 – TRGFILT Filtered input

ValueDescription
0

The external trigger input x is not filtered.

1

The external trigger input x is filtered.

Bit 28 – TRGEDGE Edge Selection

ValueNameDescription
0 FALLING_ZERO

TRGMODE = 1: TRGINx event detection on falling edge.

TRGMODE = 2, 3: TRGINx active level is 0

1 RISING_ONE

TRGMODE = 1: TRGINx event detection on rising edge.

TRGMODE = 2, 3: TRGINx active level is 1

Bits 25:24 – TRGMODE[1:0] External Trigger Mode

ValueNameDescription
0 OFF

External trigger is not enabled.

1 MODE1

External PWM Reset Mode

2 MODE2

External PWM Start Mode

3 MODE3

Cycle-by-cycle Duty Mode

Bits 23:0 – MAXCNT[23:0] Maximum Counter value

Maximum channel x counter value measured at the TRGINx event since the last read of the register.

At the TRGINx event, if the channel x counter value is greater than the stored MAXCNT value, then MAXCNT is updated by the channel x counter value.