36.5.4.1 Self-Refresh Mode
This mode is activated by configuring the Low-power Command bit (LPCB) to 1 in the MPDDRC Low-Power Register (MPDDRC_LPR).
Self-refresh mode is used in Power-down mode, that is, when no access to the DDR-SDRAM device is possible. In this case, power consumption is very low. In Self-refresh mode, the DDR-SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. During the self-refresh period, CKE is driven low. As soon as the DDR-SDRAM device is selected, the MPDDRC provides a sequence of commands and exits Self-refresh mode.
The MPDDRC re-enables Self-refresh mode as soon as the DDR-SDRAM device is not selected. It is possible to define when Self-refresh mode is to be enabled by configuring the TIMEOUT field in the MPDDRC_LPR:
0: Self-refresh mode is enabled as soon as the DDR-SDRAM device is not selected.
1: Self-refresh mode is enabled 64 clock cycles after completion of the last access.
2: Self-refresh mode is enabled 128 clock cycles after completion of the last access.
This controller also interfaces the low-power DDR-SDRAM. To optimize power consumption, the Low-Power DDR SDRAM provides programmable self-refresh options comprised of Partial Array Self-refresh (full, half, quarter and 1/8 and 1/16 array).
Disabled banks are not refreshed in Self-refresh mode. This feature permits to reduce the self-refresh current. In case of low-power DDR1-SDRAM, the Extended Mode register controls this feature. It includes Temperature Compensated Self-refresh (TSCR) and Partial Array Self-refresh (PASR) parameters and the drive strength (DS) (see MPDDRC Low-Power Register). In case of low-power DDR2-SDRAM and low-power DDR3-SDRAM, the Mode Registers 16 and 17 control this feature, including PASR Bank Mask (BK_MASK) and PASR Segment Mask (SEG_MASK) parameters and drives strength (DS) (see MPDDRC Low-power DDR2 Low-power DDR3 Low-power Register). These parameters are set during the initialization phase. After initialization, as soon as the PASR/DS/TCSR fields or BK_MASK/SEG_MASK/DS are modified, the memory device Extended Mode register or Mode registers 3/16/17 are automatically accessed. Thus if MPDDRC does not share an external bus with another controller, PASR/DS/TCSR and BK_MASK/SEG_MASK/DS bits are updated before entering Self-refresh mode or during a refresh command. If MPDDRC does share an external bus with another controller, PASR/DS/TCSR and BK_MASK/SEG_MASK/DS bits are also updated during a pending read or write access. This type of update depends on the UPD_MR bit (see MPDDRC Low-Power Register).
The low-power DDR1-SDRAM must remain in Self-refresh mode during the minimum of TRFC periods (see MPDDRC Timing Parameter 1 Register), and may remain in Self-refresh mode for an indefinite period.
The DDR2-SDRAM must remain in Self-refresh mode during the minimum of tCKE periods (refer to the memory device data sheet), and may remain in Self-refresh mode for an indefinite period.
The low-power DDR2-SDRAM and low-power DDR3-SDRAM must remain in Self-refresh mode for the minimum of tCKESR periods (refer to the memory device data sheet) and may remain in Self-refresh mode for an indefinite period.
The DDR3-SDRAM must remain in Self-refresh mode for the minimum of tCKESR periods (refer to the memory device data sheet) and may remain in Self-refresh mode for an indefinite period.
