35.1.5.5 2x16-bit LPDDR2/LPDDR3

The schematic below is given for LPDDR2 but it is also valid for LPDDR3.
Figure 35-7. 2x16-bit LPDDR2 Hardware Configuration
CAx LPDDR2/LPDDR3 signals are to be connected as indicated in the table below.
Table 35-3. CAx LPDDR2 Signal Connection
DDR Controller SignalLPDDR2 Signal
RASCA0
CASCA1
WECA2
DDR_A0CA3
DDR_A1CA4
DDR_A2CA5
DDR_A3CA6
DDR_A4CA7
DDR_A5CA8
DDR_A6CA9
Higher addressesHigher CAs