| VDDIODDR |
Power Supply of memory interface |
Power |
– |
| DDR_VREF |
Reference Voltage |
Input |
– |
| DDR_CAL |
Calibration reference |
Input |
– |
| DDR_D[31:0] |
Data Bus |
I/O |
– |
| DDR_A[13:0] |
Address Bus |
Output |
– |
| DDR_DQM[3:0] |
Data Mask |
Output |
– |
| DDR_DQS[3:0] |
Data Strobe |
I/O |
– |
| DDR_DQSN[3:0] |
Negative Data Strobe |
I/O |
– |
| DDR_CS |
Chip Select |
Output |
Low |
| DDR_RESETN |
DDR3 Active Low Asynchronous Reset |
Output |
Low |
| DDR_CLK, DDR_CLKN |
Differential Clock |
Output |
– |
| DDR_CKE |
Clock enable |
Output |
High |
| DDR_RAS |
Row signal |
Output |
Low |
| DDR_CAS |
Column signal |
Output |
Low |
| DDR_WE |
Write enable |
Output |
Low |
| DDR_BA[2:0] |
Bank Select |
Output |
– |
