15.5.6 L2CC Data RAM Latency Control Register
The L2 Cache Controller (L2CC) must be disabled in the L2CC Control Register prior to any write access to this register.
| Name: | L2CC_DRCR |
| Offset: | 0x10C |
| Reset: | 0x00000111 |
| Property: | Read/Write in Secure mode, Read-only in Non-secure mode |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DWRLAT[2:0] | |||||||||
| Access | |||||||||
| Reset | 0 | 0 | 1 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DRDLAT[2:0] | DSETLAT[2:0] | ||||||||
| Access | |||||||||
| Reset | 0 | 0 | 1 | 0 | 0 | 1 | |||
Bits 10:8 – DWRLAT[2:0] Write Access Latency
Latency to Data RAM is the programmed value + 1.
Default value is 0.