36.6.2 DDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width

Table 36-15. Sequential Mapping DDR-SDRAM Configuration Mapping: 2K Rows, 512/1024/2048 Columns, 4 Banks
CPU Address Line
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[10:0] Column[8:0] M[1:0]
Bk[1:0] Row[10:0] Column[9:0] M[1:0]
Bk[1:0] Row[10:0] Column[10:0] M[1:0]
Table 36-16. Interleaved Mapping DDR-SDRAM Configuration Mapping: 2K Rows, 512/1024/2048 Columns, 4 Banks
CPU Address Line
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[10:0] Bk[1:0] Column[8:0] M[1:0]
Row[10:0] Bk[1:0] Column[9:0] M[1:0]
Row[10:0] Bk[1:0] Column[10:0] M[1:0]
Table 36-17. Sequential Mapping DDR-SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns, 4 Banks
CPU Address Line
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[11:0] Column[7:0] M[1:0]
Bk[1:0] Row[11:0] Column[8:0] M[1:0]
Bk[1:0] Row[11:0] Column[9:0] M[1:0]
Bk[1:0] Row[11:0] Column[10:0] M[1:0]
Table 36-18. Interleaved Mapping DDR-SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns, 4 Banks
CPU Address Line
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[11:0] Bk[1:0] Column[7:0] M[1:0]
Row[11:0] Bk[1:0] Column[8:0] M[1:0]
Row[11:0] Bk[1:0] Column[9:0] M[1:0]
Row[11:0] Bk[1:0] Column[10:0] M[1:0]
Table 36-19. Sequential Mapping DDR-SDRAM Configuration Mapping: 8K Rows, 512/1024/2048 Columns, 4 Banks
CPU Address Line
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[12:0] Column[8:0] M[1:0]
Bk[1:0] Row[12:0] Column[9:0] M[1:0]
Bk[1:0] Row[12:0] Column[10:0] M[1:0]
Table 36-20. Interleaved Mapping DDR-SDRAM Configuration Mapping: 8K Rows, 512/1024/2048 Columns, 4 Banks
CPU Address Line
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[12:0] Bk[1:0] Column[8:0] M[1:0]
Row[12:0] Bk[1:0] Column[9:0] M[1:0]
Row[12:0] Bk[1:0] Column[10:0] M[1:0]
Table 36-21. Sequential Mapping DDR-SDRAM Configuration Mapping: 8K Rows, 512/1024 Columns, 8 Banks
CPU Address Line
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[2:0] Row[12:0] Column[8:0] M[1:0]
Bk[2:0] Row[12:0] Column[9:0] M[1:0]
Table 36-22. Interleaved Mapping DDR-SDRAM Configuration Mapping: 8K Rows, 512/1024 Columns, 8 Banks
CPU Address Line
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[12:0] Bk[2:0] Column[8:0] M[1:0]
Row[12:0] Bk[2:0] Column[9:0] M[1:0]
Table 36-23. Sequential Mapping DDR-SDRAM Configuration Mapping: 16K Rows, 1024 Columns, 4 Banks
CPU Address Line
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[13:0] Column[9:0] M[1:0]
Table 36-24. Interleaved Mapping DDR-SDRAM Configuration Mapping: 16K Rows, 1024 Columns, 4 Banks
CPU Address Line
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[13:0] Bk[1:0] Column[9:0] M[1:0]
Table 36-25. Sequential Mapping DDR-SDRAM Configuration Mapping: 16K Rows, 1024 Columns, 8 Banks
CPU Address Line
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[2:0] Row[13:0] Column[9:0] M[1:0]
Table 36-26. Interleaved Mapping DDR-SDRAM Configuration Mapping: 16K Rows, 1024 Columns, 8 Banks
CPU Address Line
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[13:0] Bk[2:0] Column[9:0] M[1:0]