66.7.11 ADC Interrupt Mask Register
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
Name: | ADC_IMR |
Offset: | 0x2C |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | NOPEN | PEN | | | COMPE | GOVRE | DRDY | |
Access | | R | R | | | R | R | R | |
Reset | | 0 | 0 | | | 0 | 0 | 0 | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | PRDY | YRDY | XRDY | LCCHG | | | | |
Access | | R | R | R | R | | | | |
Reset | | 0 | 0 | 0 | 0 | | | | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | EOC11 | EOC10 | EOC9 | EOC8 | |
Access | | | | | R | R | R | R | |
Reset | | | | | 0 | 0 | 0 | 0 | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EOC7 | EOC6 | EOC5 | EOC4 | EOC3 | EOC2 | EOC1 | EOC0 | |
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 30 – NOPEN No Pen Contact Interrupt Mask
Bit 29 – PEN Pen Contact Interrupt Mask
Bit 26 – COMPE Comparison Event Interrupt Mask
Bit 25 – GOVRE General Overrun Error Interrupt Mask
Bit 24 – DRDY Data Ready Interrupt Mask
Bit 22 – PRDY Touchscreen Measure Pressure Ready Interrupt Mask
Bit 21 – YRDY Touchscreen Measure YPOS Ready Interrupt Mask
Bit 20 – XRDY Touchscreen Measure XPOS Ready Interrupt Mask
Bit 19 – LCCHG Last Channel Change Interrupt Disable
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – EOCx End of Conversion Interrupt Mask x