51.10.1 DLL and Sampling Point

In SD/SDIO SDR104 mode (SDMMC_HC2R.VS18EN = 1 and SDMMC_HC2R.UHSMS = 3) or e.MMC HS200 mode (HS200EN = B(hexa)), a tuning procedure must be performed first in order to adjust the sampling point for read transactions. For more details regarding the basic tuning procedure, see section “Sampling Clock Tuning Procedure” in the “SD Host Controller Simplified Specification V3.00” .

As the position of data and command coming from the device varies, a DLL is used to generate an accurate sampling point (DLL_CLKOUT) (see the figure below).

Figure 51-3. DLL Sampling Point

The minimum SDLCK frequency is 100 MHz when SD/SDIO SDR104 or e.MMC HS200 is selected.

The sampling point can be selected to be located at 50% or 75% of the data window to anticipate the effect of the temperature rise. If SDMMC_TUNCR.SMPLPT is cleared, the sampling point is centered (50% of the data window). If SDMMC_TUNCR.SMPLPT is set to ‘1’, the sampling point is set at 75% of the data window (see the figure below).

Figure 51-4. SDR104/HS200 Sampling Point Selection