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36.6.3 DDR-SDRAM Address Mapping for Low-cost Memories
Table 36-27. Sequential Mapping for DDR-SDRAM Configuration, 2K Rows, 512
Columns, 2 Banks, 16 Bits
CPU Address Line |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
Bk |
Row[10:0] |
Column[8:0] |
M0 |
Table 36-28. Interleaved Mapping for DDR-SDRAM Configuration, 2K Rows, 512
Columns, 2 Banks, 16 Bits
CPU Address Line |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
Row[10:0] |
Bk |
Column[8:0] |
M0 |
Table 36-29. Sequential Mapping for DDR-SDRAM Configuration: 4K Rows, 256
Columns, 2 Banks, 32 Bits
CPU Address Line |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
Bk |
Row[11:0] |
Column[7:0] |
M[1:0] |
Table 36-30. Interleaved Mapping for DDR-SDRAM Configuration: 4K Rows, 256
Columns, 2 Banks, 32 Bits
CPU Address Line |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
Row[11:0] |
Bk |
Column[7:0] |
M[1:0] |
Note:
- M[1:0] is the byte address inside a
32-bit word.
- Bk[2] = BA2, Bk[1] = BA1, Bk[0] =
BA0