32.2 Embedded Characteristics

The Clock Generator is made up of:

A low-power 32.768 kHz crystal oscillator
A low-power embedded 64 kHz (typical) RC oscillator generating the 32 kHz source clock
An 8 to 24 MHz crystal oscillator or a 12 to 48 MHz XRCGB crystal resonator with Bypass mode
A 12 MHz RC oscillator
A 480 MHz UTMI PLL providing a clock for the USB High-speed Device Controller
A 600 to 1200 MHz programmable PLL, provides the clock to the processor and to the peripherals
A 700 MHz fractional-N programmable audio PLL, with 22-bit frequency resolution and two independent programmable post dividers to drive the CLK_AUDIO output pin and the internal peripherals (AUDIOPLLCLK)

The Clock Generator provides the following clocks:

TD_SLCK—Slow clock driven by either the 32.768 kHz crystal oscillator or the 32 kHz source clock. This is a permanent clock.
MAINCK—Output of the Main clock oscillator selection: either 8 to 24 MHz crystal oscillator or 12 MHz RC oscillator
PLLACK—Output of the divider and the 600 to 1200 MHz programmable PLL (PLLA)
AUDIOPLLCLK—Output of the first Audio PLL post-divider, with a frequency range from 24 to 125 MHz
AUDIOPINCLK—Output of the second Audio PLL post-divider, with a frequency range from 8 to 30 MHz
UPLLCK—Output of the 480 MHz UTMI PLL (UPLL)

The Power Management Controller also provides the following operations on clocks:

8 to 24 MHz crystal oscillator clock failure detector
32.768 kHz crystal oscillator frequency monitor
Frequency counter on Main clock and an on-the-fly adjustable 12 MHz RC oscillator frequency

For more information on electrical characteristics, refer to the section “Electrical Characteristics”.