50.7.1 QSPI Control Register
| Name: | QSPI_CR |
| Offset: | 0x00 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| LASTXFER | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWRST | QSPIDIS | QSPIEN | |||||||
| Access | W | W | W | ||||||
| Reset | – | – | – |
Bit 24 – LASTXFER Last Transfer
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The chip select is deasserted after the character written in QSPI_TDR.TD has been transferred. |
Bit 7 – SWRST QSPI Software Reset
DMA channels are not affected by software reset.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Reset the QSPI. A software-triggered hardware reset of the QSPI interface is performed. |
Bit 1 – QSPIDIS QSPI Disable
As soon as QSPIDIS is set, the QSPI finishes its transfer.
All pins are set in Input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the QSPI is disabled.
If both QSPIEN and QSPIDIS are equal to one when QSPI_CR is written, the QSPI is disabled.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the QSPI. |
Bit 0 – QSPIEN QSPI Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the QSPI to transfer and receive data. |