47.7.8.6 Character Reception

When a character reception is completed, it is transferred to the Receive Holding register (FLEX_US_RHR) and the RXRDY bit in the Status register (FLEX_US_CSR) rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into FLEX_US_RHR and overwrites the previous one. The OVRE bit is cleared by writing a one to the FLEX_US_CR.RSTSTA bit.

To ensure correct behavior of the receiver in SPI Client mode, the host device sending the frame must ensure a minimum delay of one t_bit between each character transmission. The receiver does not require a falling edge of the client select line (NSS) to initiate a character reception but only a low level. However, this low level must be present on the client select line (NSS) at least one t_bit before the first serial clock cycle corresponding to the MSB bit.