| General | Removed
Preliminary |
| Description |
|
| Features |
- Power Consumption
has been updated to Down to 8μA running the Peripheral Touch
Controller
|
| Configuration Summary | Updated
the Configuration Summary |
| Ordering
Information | Updated
Ordering Information- Added AT prefix at
the start of the ordering codes
|
| Block Diagram |
- Added the
description of the connection between PORT and ARM CORTEX-M0+ CPU: ARM
SINGLE CYCLE IOBUS
- Renamed GENERIC
CLOCK to GENERIC CLOCK CONTROLLER
|
| I/O Multiplexing and
Considerations | Updated
the Table 5-1. PORT Function Multiplexing- Renamed all
GCLK/IO[x] to GCLK_IO[x]
- Updated the
description of the Serial Wire Debug Interface Pinout
section
- Added SWDIO to PA31
column G in the Table 5-1 and added a footnote
|
| Product Mapping | Changed
Peripheral to AHB-APB |
| Signal Description |
- Removed GCLK from
the heading “Generic Clock Generator”
- Renamed IO[7:0] to
GCLK_IO[7:0]
|
| Memories |
- Added a new section
Serial Number
- Software Calibration
Row changed to Software Calibration Area
- Added Figure 9-1.
Calibration and Auxiliary space
- Updated the Table
9-4. NVM Software Calibration Area Mapping
- Added the
BOD33 and BOD12 default settings
- Added DFLL48M
COARSE CAL and DFLL48M FINE CAL
- Added table
notes on rev C (Bit 40 and Bit 41) to the Table 9-3. NVM User
Row Mapping
|
| DSU - Device Service Unit |
- Updated the Table
12-7. Register Summary
- Redefined DID
register. FAMILY changed from 4 bits to 5 bits and SERIES from 8
bits to 6 bits
- Updated the
Device Identification- DID register
- Updated Family
and Series bit registers
- Updated the
Table 12-8. Device Selection. Added ATSAMD20E18A
device at 0xA.
|
| Clock
System |
- Updated the clock
names in the Figure 13-1. Clock distribution
- Updated the
description of Generic Clock generators and Generic Clocks in the
Clock Distribution
- Updated the
Figure 13-2. Example of SERCOM clock
- Synchronous
Clock Controller renamed to Main clock controller
- Updated the
descriptive content of the Read-Synchronization section
- Changed the title
“Enable Write-Synchronization” to Write-Synchronization of
CTRL.ENABLE
- Updated the content
in Clocks after Resetsection
- Renamed
GCLKMAIN to GCLK_MAIN
|
| Generic Clock Controller |
- Updated the
Overview section and renamed GCLK_PERIPH to GCLK_PERIPHERAL
throughout the data sheet
- Updated the
Features list
- Updated Figure
14-1. Device Clocking Diagram and added a figure note
- Updated links in the
sections: Power Manageme and in Clocks
- Updated the content
in the Functional Description
- Added links in
the section Initialization for GENDIV, GENCTRL and
CLKCTRL
- Updated the
Figure 14-3. Generic Clock Generator
- Renamed
“External Clock” to Generic Clock Output on I/O Pins and
updated the description
- Updated the
Figure 14-4. Generic Clock Multiplexer
- Updated the
descriptive content in the Disabling a Generic Clock”
section
- Updated the
Figure 14-5. GCLK Indirect Access. GCLK becomes
Generic Clock
- Updated links
in the sections: Run in Standby Mode and
Synchronization
- Added a table note
on the Reset of GENCTRL register
- Added a third column
“Generator Clock Source” in the tableGENCTRL Reset Value after a
Power Reset
- Updated the content
and replaced the text “if the generator is not used by the RTC” by the
“if the generator is not used by the RTC and not a source of a
'locked' generic clock” in two tables:GENCTRL Reset Value after a
User Reset and GENDIV Reset Value after a User
Reset
|
| Power Manager |
- Updated the content
Overview
- “power save
modes” is changed to “sleep modes”
- A new line is
added: “This is because during STANDBY sleep mode the internal
voltage regulator will be in low power mode”
- Updated
Featureslist
- Clock control:
“Generates” is changed to “Controls”
- Updated le content
in the Clockssection
- “This clock”
is changed to “The clock source for GCLK_MAIN”
- Updated the content
in Interrupts section
- Added: “Refer
to Nested Vector Interrupt Controller"
- Updated Register
Access Protection
- Added: “Refer
to Interrupt Flag Status and Clear - INTFLAG register for
details”
- Added: “Refer
to Reset Cause - RCAUSE register for details”
- Updated the
sections: Synchronous Clocks and Sleep Mode
Controller
- Added: "see
Table 15-4. Sleep Mode Overview"
- Updated Reset
Controller section
- “resets”
corrected to “reset”
- Updated
Initialization section
- Added: “-
refer to Reset Cause - RCAUSE register for details”
- Updated Selecting
the Synchronous Clock Division Ratio
- Added:
“(APBxSEL.APBxDIV)”
- Updated the figure
Synchronous Clock Selection and Prescaler
- Updated Clock
Ready Flag section
- “CKSEL” is
changed to “CPUSEL”
- Updated the
Peripheral Clock Masking section
- Added: “refer
to APBA Mask - APBAMASK register for details”
- The first
sentence below the figure has been changed to: “When the APB
clock for a module is not provided its registers cannot be read
or written.”
- Updated the content
Clock Failure Detector section
- “CFDEN.CTRL”
has been changed to “CTRL.CFDEN”
- Added: “Refer
to Control - CTRL register for details”
- “divided” has
been changed to “undivided”
- “is generated,
if enabled” has been changed to "is set and the corresponding
interrupt request will be generated if enabled"
- “GCLKMAIN” has
been changed to “GCLK_MAIN”
- Added: Note
3
- Updated the table
Effects of the Different Reset Events
- “GCLK” has
been changed to “Generic Clock”
- Updated the figure
Reset Controller
- Updated the table
Sleep Mode Entry and Exit
- Two notes
(“Synchronous” and “Asynchronous”) are added below the
table
- Updated the Sleep
Mode Controller section
- Updated the
text in STANDBY mode
|
| Power
Manager (cont.) |
- Updated the table
Sleep Mode Overview
- Replaced the
table with an accurate one
- Updated IDLE
Mode section
- Second bullet:
“any non-masked interrupt” changed to “the occurrence of any
interrupt that is not masked in the NVIC Controller”
- Updated STANDBY
Mode section
- “GCLK” is
changed to “Generic Clock”
- Added:
SleepWalking section
- Updated Bit 4 –
BKUPCLK: Backup Clock Select”
- “GCLKMAIN” is
changed to “GCLK_MAIN”
|
| SYSCTRL – System Controller |
- Updated the content
in Overview section
- “XOSC,
XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M, BOD33, BOD12, VREG
and VREF” is changed to “clock sources, brown out detectors,
on-chip voltage regulator and voltage reference of the
device."
- Added: “ refer
to Power and Clocks Status - PCLKSR register"
- Added:
“(INTENSET)”
- Added:
“(INTENCLR)”
- Added:
“(INTFLAG)”
- Updated the content
in Principle of Operationsection
- Added two
tables for the behavior of Oscillators and Sleep modes
- Updated Register
Access Protection
- Added: “-
refer to INFLAG
- Updated Analog
Connections section
- Changed “load.
Refer” to “load, refer”
- Updated External
Multipurpose Crystal Oscillator (XOSC) Operation section
- Changed “the
only” to “only the”
- “the XTAL
Enable bit (XOSC.XTALEN) must written to one” is changed to “a
one must be written to the XTAL Enable bit (XOSC.XTALEN)."
- Updated the content
in 32kHz External Crystal Oscillator (XOSC32K) Operation
section
- “power-on,
reset” is changed to “power-on reset (POR)”
- Added:
"XOSC32K can provide two clock outputs when connected to a
crystal.”
- Updated the content
in 8MHz Internal Oscillator (OSC8M) Operation section
- Updated the content
in 32kHz Internal Oscillator (OSC32K) Operation section
- Changed
“CALIB” to “OSC32K.CALIB”
- Changed
“non-volatile memory” to “NVM Software Calibration ROW”
- Added: “(refer
to NVM Software Calibration Area Mapping
- Updated the content
in 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
Operation section
- Added:
32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
Control - OSCULP32K register
- Updated the content
in Closed-Loop Operation section
- List #3:
Changed “device” to “DFLL”
- Below “Drift
Compensation”: “set” has been replaced by “triggered”
- The text
“shown in the SYSCTRL Block Diagram" has been
removed
|
| SYSCTRL -
System Control (cont.) |
- Updated
Additional Features
- The text “when
disabling the DFLL48M” below “Wake from Sleep Modes” has been
replaced by the text “when the DFLL is turned off”
- Updated 3.3V
Brown-Out Detector (BOD33) section
- “Brown-Out
Detector” is replaced by “BOD33”
- Updated 32kHz
Internal Oscillator (OSC32K) Control - OSC32K register
- The reference
for Bits 22:16 - CALIB[6:0] has been corrected
- Updated the table
Start-UpTime for External Multipurpose Crystal Oscillator
- Both notes for
this table has been updated/changed
- New “Note 3”
is added
- Updated the table
Start-Up Time for 32kHz External Crystal Oscillator
- Both notes for
this table has been updated/changed
- New “Note 3”
is added
- Updated the table
Start-Up Time for 32kHz Internal Oscillator
- New column for
“Number of OSC32K Clock Cycles” is added
- The values in
the column for the “old” “Number of OSC32K Clock Cycles” has
been corrected
- Both notes for
this table has been updated/changed
- New “Note 3”
is added
- Updated DFLL48M
Control - DFLLCTRL register
- For “Property”
the following has been added: “, Write-Synchronized”
- Removed
RUNSTDBY
- Updated DFLL48M
Value - DFLLVAL register
- For “Property”
the following has been added: “, Read-Synchronized”
- Updated Register
Access Protection register
- In the bullet
point the following is added: “ refer to Interrupt Flag
Status and Clear - INTFLAG register”
- Updated Principle
of Operation section
- Added: “-
refer to Control - CTRL register "and “- refer to
Interrupt Enable Clear - INTENCLR register”
- Updated the Default
Reset value in 8MHz Internal Oscillator (OSC8M) Control - OSC8M
register and fixed the RANGE bitfield
- Updated the description
of the Bit 4 DFLL Ready in Power and Clocks Status - PCLKSR
register and updated Bit
11 BOD33 Synchronization Ready
|
| WDT – Watchdog Timer |
- Updated
Intitialization
- Added: “-
refer to CTRL register”, “- refer to CONFIG
register”, and “- refer to EWCTRL regsiter”
- Updated Normal
Mode
- Added: “-
refer to Clear - CLEAR register
- Updated the
description of the Bit 2 (CTRL.WEN) in the Control - CTRL
register
- Removed
“Asynchronous Watchdog Clock Characterization”
|
| SERCOM SPI – SERCOM Serial Peripheral Interface |
- Updated the
description of the SPI Transfer Modes section
|
| RTC - Real-Time Counter |
- Updated Register
Access Protection section
- Added: “-
refer to INTFLAG register”, “- refer to READREQ
register”, “- refer to STATUS register”, and “- refer to
DBGCTRL register”
- Updated the content
in Initialization section
- Added: “-
refer to Event Control - EVCTRL register”
|
| EIC -
External Interrupt Controller |
- Updated the content
in Events section
- Added text
“External Interrupt Controller generates events as pulses”
- Updated the content
Sleep Mode Operation section
- Added text
“Using WAKEUPEN[x]=1 with INTENSET=0 is not recommended”
- Updated the content
Register Access Protection
- Added: “-
refer to INTFLAG register” and “- refer to NMIFLAG
register”
- Updated
Additional Features
- Added: “-
refer to NMICTRL register”
|
| NVMCTRL -
Non-Volatile Memory Controller |
- Updated Power
Management section
- Added: “-
refer to CTRLB register”
- Added Basic
Operations section
- Updated
Interrupts section
- Added a
reference link to Nested Vector Interrupt Controller
- Updated the
description of NVM Read section
- Updated the content
in Register Access Protection section
- Added: “- refer to
INTFLAG regsiter” and “- refer to STATUS
register”
- Updated the
description of MANW bit in CTRLB register
- Updated the
description of ERROR and READY bits in INTENCLR register
|
| PORT |
- Updated CPU Local
Bus section
- Added: “-
refer to DIR register”, “- refer to OUT register”,
“- refer to IN register", and “- refer to CTRL
register”
- Updated Principle
of Operation section
- Added: “-
refer to DIR register”, “- refer to OUT register”,
“- refer to PINCFG0 register”, “- refer to IN
register”, and “- refer to PMUX0 register”
|
| TC |
- Updated the table
Waveform Generation Operation. Switched “Clear” and “Set”
for CCO value (MPWM).
|
| ADC |
- Updated the content
in Sleep Mode Operation section
- Added “While
the CPU is sleeping, ADC conversion can only be triggered by
vents”
- Software Calibration
Row changed to Software Calibration Area
|
| AC |
- Updated the content
in Sleep Mode Operation section
- Added “While
the CPU is sleeping, single-shot comparisons are only
triggerable by events”
|
| Electrical
Characteristics |
- Updated
Disclaimer section. Removed the preliminary disclaimer
- Updated the table
Absolute maximum ratings
- Updated IVDD
and IGND max values
- Added TSTORAGE
- Updated the table
General operating conditions
- Updated the table
Current Consumption
- Added min and
max values
- Added
consumption data
- Updated IOL and IOH in the
table RevD and later normal I/O Pins Characteristics
- Updated VHYS min
value in I2C Pins Characteristics in I2C
configuration
- Duplicated all
tables in the table I/O Pin Characteristics” to differentiate
rev D (the table RevD and later normal I/O Pins
Characteristics) from rev C (the table RevC and later normal
I/O Pins Characteristics)
- Updated the table
and renamed to Voltage Regulator Electrical Characteristics
- Added
condition to VDDCORE characteristics
- Updated the table
BOD33 LEVEL Value
- Added a table
note to specify BOD33.LEVEL default production settings
- Updated the table
BOD33 Characteristics
- Added current
consumption data (IBOD33)
- ADC Characteristics:
Removed the min value of IDD from the table Operating
Conditions
- Updated the Bandgap
Gain Error min and max values in the table Differential
Mode
- DAC characteristics:
Updated IDD values and conditions in the table Operating
Conditions
- Removed the table
note from the table Bandgap (Internal 1.1V reference)
characteristics
- Updated the Accuracy
unit in the table Accuracy Characteristics
- Removed tFFP from the
tableNVM Characteristics
- Updated the table
Temperature Sensor Characteristics
- Updated the content
in Crystal Oscillator (SOSC) Characteristics section
- Added new
characterization data
- Removed fCPXIN
min value from Digital Clock Characteristics table
- Changed the title to
Digital Frequency Locked Loop (DFLL48M) Characteristics and
added table note to DFLL48M Characteristics - Closed Loop
Mode
- Updated the table
32kHz Crystal Oscillator Characteristics
- Updated IXOSC32K
- Added a table
note for “AGC on”: data are not yet available for rev D
- Added current
consumption data (IOSC32K) in the table 32kHz RC
Oscillator Characteristics
- Updated IOSC8M in the
table Internal 8MHz RC Oscillator Characteristics
|
| Package |
- Added notes to
64QFN, 48QFN and to 32QFN packages
- Updated Device
and Package Maximum Weight for 32-pin TQFP and for
32-pin QFN
- Device and
Package Maximum Weight is 100mg for TQFP32 and 90mg for
QFN32
|
