17.3.11 PORTWCLK

Signal Routing Port Clock Selection

Note: This register can only be written when the clock to the module is disabled. See Signal Routing Port Clock for details.

Name:	PORTWCLK
Offset:	0x1F2C


Bit	7	6	5	4	3	2	1	0
				CLK[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – CLK[4:0] Signal Routing Port Clock Input Selection

Table 17-2. Signal Routing Port Clock Input Selections
Value	Description
`11111-11000`	Reserved
`10111`	NCO1_OUT
`10110`	CLC4_OUT
`10101`	CLC3_OUT
`10100`	CLC2_OUT
`10011`	CLC1_OUT
`10010`	PWM2S1P2_OUT
`10001`	PWM2S1P1_OUT
`10000`	PWM1S1P2_OUT
`01111`	PWM1S1P1_OUT
`01110`	CCP2_OUT
`01101`	CCP1_OUT
`01100`	TMR1_overflow
`01011`	TMR0_overflow
`01010`	TMR4_OUT
`01001`	TMR2_OUT
`01000`	CLKREF_OUT
`00111`	EXTOSC
`00110`	SOSC
`00101`	MFINTOSC (31.25 kHz)
`00100`	MFINTOSC (500 kHz)
`00011`	LFINTOSC
`00010`	HFINTOSC
`00001`	F_OSC
`00000`	PORTWCLKPPS

Reset States:

POR/BOR = 00000

All Other Resets = 00000

This register can only be written when the clock to the module is disabled. See Signal Routing Port Clock for details.

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