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31.8.4 CLCnSEL0 Generic CLCn Data 1 Select
Register Name: CLCnSEL0 Offset: 0x068E
Bit 7 6 5 4 3 2 1 0 D1S[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x
Bits 6:0 – D1S[6:0] CLCn Data1 Input Selection
Table 31-2. CLC Input Selection DyS Input Source DyS (cont.) Input Source (cont.) [0] 0000 0000 CLCIN0PPS [23] 0001 0111 PWM1S1P2_OUT [1] 0000 0001 CLCIN1PPS [24] 0001 1000 PWM2S1P1_OUT [2] 0000 0010 CLCIN2PPS [25] 0001 1001 PWM2S1P2_OUT [3] 0000 0011 CLCIN3PPS [26] 0001 1010 NCO1_OUT [4] 0000 0100 FOSC [27] 0001 1011 C1_OUT [5] 0000 0101 HFINTOSC [28] 0001 1100 CLP1_OUT [6] 0000 0110 LFINTOSC [29] 0001 1101 ZCD_OUT [7] 0000 0111 MFINTOSC (500 kHz) [30] 0001 1110 IOCIF [8] 0000 1000 MFINTOSC (31.25 kHz) [31] 0001 1111 CLC1_OUT [9] 0000 1001 — [32] 0010 0000 CLC2_OUT [10] 0000 1010 SOSC [33] 0010 0001 CLC3_OUT [11] 0000 1011 EXTOSC [34] 0010 0010 CLC4_OUT [12] 0000 1100 ADCRC [35] 0010 0011 TX1/CK1 [13] 0000 1101 CLKR_OUT [36] 0010 0100 TX2/CK2 [14] 0000 1110 TMR0_Overflow [37] 0010 0101 SDA1/SDO1 [15] 0000 1111 TMR1_Overflow [38] 0010 0110 SCL1/SCK1 [16] 0001 0000 TMR2_Postscaled_OUT [39] 0010 0111 SDA2/SDO2 [17] 0001 0001 TMR3_Overflow [40] 0010 1000 SCL2/SCK2 [18] 0001 0010 TMR4_Postscaled_OUT [41] 0010 1001 CWG1A_OUT [19] 0001 0011 — [42] 0010 1010 CWG1B_OUT [20] 0001 0100 CCP1_OUT [43] 0010 1011 — [21] 0001 0101 CCP2_OUT ... — [22] 0001 0110 PWM1S1P1_OUT [127] 0111 1111
Reset States: POR/BOR = xxxxxxx All Other Resets = uuuuuuu
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