3.2 Sample Duration

A suitable ADC sample duration can either be calculated based on the impulse response of the circuit, as shown in Section Input Impedance, or found by tuning the sample duration in firmware until a stable output from the ADC conversion is achieved.

The sample duration for this ADC can be a maximum of 256 ADC clock (CLK_ADC) cycles, and is configured using the Sample Duration (SAMPDUR) bit field in the Control E (ADCn.CTRLE) register. The sample duration is SAMPDUR + 0.5 (CLK_ADC) cycles when the PGA is disabled, and SAMPDUR + 1 (CLK_ADC) when the PGA is enabled. If the input impedance is very high, increasing the ADC prescaler can also be used to further increase the sample duration.

Minimum sample duration is configured as shown in the following code snippet. The calculations are based on the CPU clock running at 16 MHz, with PGA disabled.
ADC0.CTRLB = ADC_PRESC_DIV2_gc; /* ADC clock: 8 MHz */
ADC0.CTRLE = 0; /* Sample Duration: (0 + 0.5) / 8 MHz = 0.06 µS */
Maximum sample duration is configured as shown in the following code snippet. The calculations are based on the CPU clock running at 16 MHz, with PGA disabled.
ADC0.CTRLB = ADC_PRESC_DIV40_gc; /* ADC clock: 400 kHz */
ADC0.CTRLE = 255; /* Sample Duration: (255 + 0.5) / 400 kHz = 639 µS */