5.3 Left Adjust

The Left Adjust (LEFTADJ) bit in the Control F (ADCn.CTRLF) register enables left-shift of the output data in the modes where this is supported. If enabled, this will left-shift the output from both the Result and the Sample registers. It is configured as shown in the following code snippet:

ADC0.CTRLF = ADC_LEFTADJ_bm; /* Enable Left Adjust bit */

Left adjust is available in ADC mode 3, Series Accumulation with Scaling.

The following tables show how the left adjust feature affects the Result register output format in Single-Ended and Differential modes.

Table 5-1. RESULT Register – Single-Ended Mode – ADC Mode 3
LEFTADJRES[31:24]RES[23:16]RES[15:12]RES[11:8]RES[7:0]
00x00Scaled accumulation[15:0]
10x00Scaled accumulation[15:0](1)
Table 5-2. RESULT Register – Differential Mode – ADC Mode 3
LEFTADJRES[31:24]RES[23:16]RES[15:12]RES[11:8]RES[7:0]
0Sign ExtensionSigned Scaled accumulation[15:0]
1Sign ExtensionSigned Scaled accumulation[15:0](1)

If SAMPNUM < 4, the result is left-shifted 4 - SAMPNUM bits such that bit 15 is the MSb. If SAMPNUM > 4, the scaling feature of the ADC mode right-shifts the result by SAMPNUM - 4 bits.

Example 1: SAMPNUM = 3 (Accumulation with 8 samples)

When the Left Adjust bit is 0, ADCn.SAMPLE = 0xFFF for all samples, and 8 samples are accumulated, the accumulated value in ADCn.RESULT is 8 x 4095 = 0x7FF8.

After enabling the Left Adjust bit, the result will be left-shifted by 4 - SAMPNUM = 1 bit (SAMPNUM is 3 to accumulate 8 samples). So by left-shifting 0x7FF8 by 1 bit, ADCn.RESULT = 0xFFF0.

Example 2: SAMPNUM = 5 (Accumulation with 32 samples)

When the Left Adjust bit is 0, ADCn.SAMPLE = 0xFFF for all samples, and 32 samples are accumulated, the accumulated value is 32 x 4095 = 0x1FFE0.

In Scaling mode, the result will be right-shifted by SAMPNUM - 4 = 1 bit (SAMPNUM is 5 to accumulate 32 samples). So by right-shifting 0x1FFE0 by 1 bit, ADCn.RESULT = 0xFFF0.

The following table show how the left adjust feature affects the Sample register output format in Single-Ended and Differential modes.

Table 5-3. SAMPLE Register – Single-Ended/Differential Mode – ADC Mode 3
LEFTADJDIFFSAMPLE[15:12]SAMPLE[11:8]SAMPLE[7:0]
000x00Conversion[11:0]
1Sign extensionSigned conversion[11:0]
10Conversion[11:0] << 4
1Signed conversion[11:0] << 4

For example, if the Left Adjust feature is disabled and the ADCn.SAMPLE value is 0x0FFF, the corresponding ADCn.SAMPLE value when Left Adjust is enabled is 0xFFF0.