4.3 Conversion Time
The conversion time for a single sample is calculated by:
For example, given initialization = 60 μs, SAMPDUR = 2 an fCLk_ADC = 1 MHz, the conversion time for each sample is given by:
With the Low Latency (LOWLAT) bit written to ‘1’ in the
Control A (ADCn.CTRLE) register, the initialization time is only needed once upon
enabling the ADC. After that, the example above will give a sample conversion time of
17.5 µs.
The sampling period of the ADC is configured through the Sample Duration
(SAMPDUR) bit field in the Control E (ADCn.CTRLE) register as (SAMPDUR + ½ ) CLK_ADC
cycles.
ADC0.CTRLE = 2; /* Sample duration configured to 2 */ If PGA is used, the input sample duration is (SAMPDUR + 1) CLK_ADC cycles,
while the ADC PGA Sample Duration (ADCPGASAMPDUR) bit field in the PGA Control
(ADCn.PGACTRL) register controls how long the ADC samples the
PGA.
ADC0.PGACTRL = ADC_ADCPGASAMPDUR_15CLK_gc; /* 15 CLK_ADC cycles */