30.5.10 ASI System Status
| Name: | ASI_SYS_STATUS |
| Offset: | 0x0B |
| Reset: | 0x01 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RSTSYS | INSLEEP | NVMPROG | UROWPROG | LOCKSTATUS | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 1 |
Bit 5 – RSTSYS System Reset Active
If this bit is set, there is an active Reset on the system domain. If this bit is cleared, the system is not in Reset.
This bit is cleared on read.
A Reset held from the ASI_RESET_REQ register will also affect this bit.
Bit 4 – INSLEEP System Domain in Sleep
If this bit is set, the system domain is in IDLE or deeper Sleep mode. If this bit is cleared, the system is not in Sleep.
Bit 3 – NVMPROG Start NVM Programming
If this bit is set, NVM Programming can start from the UPDI.
When the UPDI is done, it must reset the system through the UPDI Reset register.
Bit 2 – UROWPROG Start User Row Programming
If this bit is set, User Row Programming can start from the UPDI.
When the UPDI is done, it must write the UROWWRITE_FINAL bit in ASI_SYS_CTRLA.
Bit 0 – LOCKSTATUS NVM Lock Status
If this bit is set, the device is locked. If a Chip Erase is done, and the Lockbits are cleared, this bit will read as ‘0’.