36.7 ADC - 10-Bit Single Ended Mode

Figure 36-95. Gain Error vs. VREFA (ADC Single Ended Mode @170 ksps, VVDD = 3.0V)
Figure 36-96. Gain Error vs. Sample Rate (ADC Single Ended Mode, VREFA = VDD = 3.0V)
Figure 36-97. Offset Error vs. VREFA (ADC Single Ended Mode @170 ksps, VVDD = 3.0V)
Figure 36-98. Offset Error vs. Sample Rate (ADC Single Ended Mode, VREFA = VDD = 3.0V)
Figure 36-99. DNL vs. ADC code (ADC Single Ended Mode @170 ksps, VDD = 3.0V)
Figure 36-100. DNL vs. Sample Rate (ADC Single Ended Mode, VREFA = VDD = 3.0V, T = 85°C)
Figure 36-101. DNL vs. VREFA (ADC Single Ended Mode @170 ksps, VDD = 3.0V, T = 85°C)
Figure 36-102. INL vs. ADC code (ADC Single Ended Mode @170 ksps, VDD = 3.0V)
Figure 36-103. INL vs. Sample Rate (ADC Single Ended Mode, VREFA = VDD = 3.0V, T = 85°C)
Figure 36-104. INL vs. VREFA (ADC Single Ended Mode @170 ksps, VDD = 3.0V, T = 85°C)