29.3.3 Interrupts
| Name | Vector Description | Conditions |
|---|---|---|
| NMI | Non-Maskable Interrupt | CRC failure |
When the interrupt condition occurs, the OK flag in the Status (CRCSCAN.STATUS) register is
cleared to ‘0’.
A Non-Maskable Interrupt (NMI) is enabled by writing a ‘1’ to the
respective Enable (NMIEN) bit in the Control A (CRCSCAN.CTRLA) register, but can only be
disabled with a System Reset. An NMI is generated when the OK flag in the CRCSCAN.STATUS
register is cleared, and the NMIEN bit is ‘1’. The NMI request remains
active until next System Reset and cannot be disabled.
An NMI can be triggered even if interrupts are not globally enabled.