6 Package and Ballout

The SAMA5D2 SIP is available in the packages listed below.

Important: SAMA5D2 DDR2 SIP devices are not pin-to-pin compatible with SAMA5D2 devices.

Table 6-1. Packages
Package Name	Ball Count	Ball Pitch	Package Size
TFBGA196	196	0.75 mm	11 x 11 (mm)
TFBGA289⁽¹⁾	289	0.8 mm	14 x 14 (mm)
TFBGA361⁽²⁾	361	0.8 mm	16 x 16 (mm)

Note:

512 Mbit and 1 Gbit DDR2 in TFBGA289 have the same ballout.
1 Gbit and 2 Gbit LPDDR2 in TFBGA361 have the same ballout.

Table 6-2. Ball Description
361-ball BGA	289-ball BGA	196-ball BGA	Power Rail	I/O Type	Primary		Alternate		PIO Peripheral				Reset State (Signal, Dir, PU, PD, HiZ, ST)⁽¹⁾
361-ball BGA	289-ball BGA	196-ball BGA	Power Rail	I/O Type	Signal	Dir	Signal	Dir	Func	Signal	Dir	IO Set	Reset State (Signal, Dir, PU, PD, HiZ, ST)⁽¹⁾
W11	U13	M8	VDDSDMMC	GPIO_EMMC	PA0	I/O	–	–	A	SDMMC0_CK	I/O	1	PIO, I, PU, ST
									B	QSPI0_SCK	O	1
									F	D0	I/O	2
R9	N7	F7	VDDSDMMC	GPIO_EMMC	PA1	I/O	–	–	A	SDMMC0_CMD	I/O	1	PIO, I, PU, ST
									B	QSPI0_CS	O	1
									F	D1	I/O	2
W12	U14	L8	VDDSDMMC	GPIO_EMMC	PA2	I/O	–	–	A	SDMMC0_DAT0	I/O	1	PIO, I, PU, ST
									B	QSPI0_IO0	I/O	1
									F	D2	I/O	2
V11	T13	G8	VDDSDMMC	GPIO_EMMC	PA3	I/O	–	–	A	SDMMC0_DAT1	I/O	1	PIO, I, PU, ST
									B	QSPI0_IO1	I/O	1
									F	D3	I/O	2
W14	U15	K8	VDDSDMMC	GPIO_EMMC	PA4	I/O	–	–	A	SDMMC0_DAT2	I/O	1	PIO, I, PU, ST
									B	QSPI0_IO2	I/O	1
									F	D4	I/O	2
V10	U16	P9	VDDSDMMC	GGPIO_EMMC	PA5	I/O	–	–	A	SDMMC0_DAT3	I/O	1	PIO, I, PU, ST
									B	QSPI0_IO3	I/O	1
									F	D5	I/O	2
W15	U17	P10	VDDSDMMC	GPIO_EMMC	PA6	I/O	–	–	A	SDMMC0_DAT4	I/O	1	PIO, I, PU, ST
									B	QSPI1_SCK	O	1
									D	TIOA5	I/O	1
									E	FLEXCOM2_IO0	I/O	1
									F	D6	I/O	2
W16	R11	P11	VDDSDMMC	GPIO_EMMC	PA7	I/O	–	–	A	SDMMC0_DAT5	I/O	1	PIO, I, PU, ST
									B	QSPI1_IO0	I/O	1
									D	TIOB5	I/O	1
									E	FLEXCOM2_IO1	I/O	1
									F	D7	I/O	2
V12	R9	K9	VDDSDMMC	GPIO_EMMC	PA8	I/O	–	–	A	SDMMC0_DAT6	I/O	1	PIO, I, PU, ST
									B	QSPI1_IO1	I/O	1
									D	TCLK5	I	1
									E	FLEXCOM2_IO2	I/O	1
									F	NWE/NANDWE	O	2
V16	P8	J9	VDDSDMMC	GPIO_EMMC	PA9	I/O	–	–	A	SDMMC0_DAT7	I/O	1	PIO, I, PU, ST
									B	QSPI1_IO2	I/O	1
									D	TIOA4	I/O	1
									E	FLEXCOM2_IO3	O	1
									F	NCS3	O	2
V14	R10	N14	VDDSDMMC	GPIO_EMMC	PA10	I/O	–	–	A	SDMMC0_RSTN	O	1	PIO, I, PU, ST
									B	QSPI1_IO3	I/O	1
									D	TIOB4	I/O	1
									E	FLEXCOM2_IO4	O	1
									F	A21/NANDALE	O	2
L18	P15	N13	VDDIOP1	GPIO	PA11	I/O	–	–	A	SDMMC0_1V8SEL	O	1	PIO, I, PU, ST
									B	QSPI1_CS	O	1
									D	TCLK4	I	1
									F	A22/NANDCLE	O	2
T16	N17	L12	VDDIOP1	GPIO	PA12	I/O	–	–	A	SDMMC0_WP	I	1	PIO, I, PU, ST
									B	IRQ	I	1
									F	NRD/NANDOE	O	2
K18	P16	M14	VDDIOP1	GPIO	PA13	I/O	–	–	A	SDMMC0_CD	I	1	PIO, I, PU, ST
									E	FLEXCOM3_IO1	I/O	1
									F	D8	I/O	2
R19	M17	J10	VDDIOP1	GPIO_QSPI	PA14	I/O	–	–	A	SPI0_SPCK	I/O	1	PIO, I, PU, ST
									B	TK1	I/O	1
									C	QSPI0_SCK	O	2
									D	I2SC1_MCK	O	2
									E	FLEXCOM3_IO2	I/O	1
									F	D9	I/O	2
L17	N16	L14	VDDIOP1	GPIO	PA15	I/O	–	–	A	SPI0_MOSI	I/O	1	PIO, I, PU, ST
									B	TF1	I/O	1
									C	QSPI0_CS	O	2
									D	I2SC1_CK	I/O	2
									E	FLEXCOM3_IO0	I/O	1
									F	D10	I/O	2
N19	M11	H14	VDDIOP1	GPIO_IO	PA16	I/O	–	–	A	SPI0_MISO	I/O	1	PIO, I, PU, ST
									B	TD1	O	1
									C	QSPI0_IO0	I/O	2
									D	I2SC1_WS	I/O	2
									E	FLEXCOM3_IO3	O	1
									F	D11	I/O	2
M16	N14	K14	VDDIOP1	GPIO_IO	PA17	I/O	–	–	A	SPI0_NPCS0	I/O	1	PIO, I, PU, ST
									B	RD1	I	1
									C	QSPI0_IO1	I/O	2
									D	I2SC1_DI0	I	2
									E	FLEXCOM3_IO4	O	1
									F	D12	I/O	2
V19	T16	L9	VDDIOP1	GPIO_IO	PA18	I/O	–	–	A	SPI0_NPCS1	O	1	PIO, I, PU, ST
									B	RK1	I/O	1
									C	QSPI0_IO2	I/O	2
									D	I2SC1_DO0	O	2
									E	SDMMC1_DAT0	I/O	1
									F	D13	I/O	2
V15	T15	P12	VDDIOP1	GPIO_IO	PA19	I/O	–	–	A	SPI0_NPCS2	O	1	PIO, I, PU, ST
									B	RF1	I/O	1
									C	QSPI0_IO3	I/O	2
									D	TIOA0	I/O	1
									E	SDMMC1_DAT1	I/O	1
									F	D14	I/O	2
T10	P9	H9	VDDIOP1	GPIO_IO	PA20	I/O	–	–	A	SPI0_NPCS3	O	1	PIO, I, PU, ST
									D	TIOB0	I/O	1
									E	SDMMC1_DAT2	I/O	1
									F	D15	I/O	2
U19	P10	G9	VDDIOP1	GPIO_IO	PA21	I/O	–	–	A	IRQ	I	2	PIO, I, PU, ST
									B	PCK2	O	3
									D	TCLK0	I	1
									E	SDMMC1_DAT3	I/O	1
									F	NANDRDY	I	2
V17	T17	K10	VDDIOP1	GPIO_QSPI	PA22	I/O	–	–	A	FLEXCOM1_IO2	I/O	1	PIO, I, PU, ST
									B	D0	I/O	1
									C	TCK	I	4
									D	SPI1_SPCK	I/O	2
									E	SDMMC1_CK	I/O	1
									F	QSPI0_SCK	O	3
U18	T14	G10	VDDIOP1	GPIO	PA23	I/O	–	–	A	FLEXCOM1_IO1	I/O	1	PIO, I, PU, ST
									B	D1	I/O	1
									C	TDI	I	4
									D	SPI1_MOSI	I/O	2
									F	QSPI0_CS	O	3
W17	R17	P13	VDDIOP1	GPIO_IO	PA24	I/O	–	–	A	FLEXCOM1_IO0	I/O	1	PIO, I, PU, ST
									B	D2	I/O	1
									C	TDO	O	4
									D	SPI1_MISO	I/O	2
									F	QSPI0_IO0	I/O	3
W18	R16	H10	VDDIOP1	GPIO_IO	PA25	I/O	–	–	A	FLEXCOM1_IO3	O	1	PIO, I, PU, ST
									B	D3	I/O	1
									C	TMS	I	4
									D	SPI1_NPCS0	I/O	2
									F	QSPI0_IO1	I/O	3
U14	P17	L10	VDDIOP1	GPIO_IO	PA26	I/O	–	–	A	FLEXCOM1_IO4	O	1	PIO, I, PU, ST
									B	D4	I/O	1
									C	NTRST	I	4
									D	SPI1_NPCS1	O	2
									F	QSPI0_IO2	I/O	3
M18	R15	P14	VDDIOP1	GPIO_IO	PA27	I/O	–	–	A	TIOA1	I/O	2	PIO, I, PU, ST
									B	D5	I/O	1
									C	SPI0_NPCS2	O	2
									D	SPI1_NPCS2	O	2
									E	SDMMC1_RSTN	O	1
									F	QSPI0_IO3	I/O	3
U13	R14	N12	VDDIOP1	GPIO	PA28	I/O	–	–	A	TIOB1	I/O	2	PIO, I, PU, ST
									B	D6	I/O	1
									C	SPI0_NPCS3	O	2
									D	SPI1_NPCS3	O	2
									E	SDMMC1_CMD	I/O	1
									F	CLASSD_L0	O	1
U16	P14	M12	VDDIOP1	GPIO	PA29	I/O	–	–	A	TCLK1	I	2	PIO, I, PU, ST
									B	D7	I/O	1
									C	SPI0_NPCS1	O	2
									E	SDMMC1_WP	I	1
									F	CLASSD_L1	O	1
U12	R13	N11	VDDIOP1	GPIO	PA30	I/O	–	–	B	NWE/NANDWE	O	1	PIO, I, PU, ST
									C	SPI0_NPCS0	I/O	2
									D	PWMH0	O	1
									E	SDMMC1_CD	I	1
									F	CLASSD_L2	O	1
U17	P13	M11	VDDIOP1	GPIO	PA31	I/O	–	–	B	NCS3	O	1	PIO, I, PU, ST
									C	SPI0_MISO	I/O	2
									D	PWML0	O	1
									F	CLASSD_L3	O	1
C7	F5	E6	VDDIOP0	GPIO	PB0	I/O	–	–	B	A21/NANDALE	O	1	PIO, I, PU, ST
									C	SPI0_MOSI	I/O	2
									D	PWMH1	O	1
A9	C8	D6	VDDIOP0	GPIO	PB1	I/O	–	–	B	A22/NANDCLE	O	1	PIO, I, PU, ST
									C	SPI0_SPCK	I/O	2
									D	PWML1	O	1
									F	CLASSD_R0	O	1
A10	C7	C6	VDDIOP0	GPIO	PB2	I/O	–	–	B	NRD/NANDOE	O	1	PIO, I, PU, ST
									D	PWMFI0	I	1
									F	CLASSD_R1	O	1
A11	B8	C5	VDDIOP0	GPIO	PB3	I/O	–	–	A	URXD4	I	1	PIO, I, PU, ST
									B	D8	I/O	1
									C	IRQ	I	3
									D	PWMEXTRG1	I	1
									F	CLASSD_R2	O	1
A12	B7	D5	VDDIOP0	GPIO	PB4	I/O	–	–	A	UTXD4	O	1	PIO, I, PU, ST
									B	D9	I/O	1
									C	FIQ	I	4
									F	CLASSD_R3	O	1
A7	A10	D7	VDDIOP0	GPIO_QSPI	PB5	I/O	–	–	A	TCLK2	I	1	PIO, I, PU, ST
									B	D10	I/O	1
									C	PWMH2	O	1
									D	QSPI1_SCK	O	2
									F	GTSUCOMP	O	3
B7	A9	C8	VDDIOP0	GPIO	PB6	I/O	–	–	A	TIOA2	I/O	1	PIO, I, PU, ST
									B	D11	I/O	1
									C	PWML2	O	1
									D	QSPI1_CS	O	2
									F	GTXER	O	3
C5	D5	D9	VDDIOP0	GPIO_IO	PB7	I/O	–	–	A	TIOB2	I/O	1	PIO, I, PU, ST
									B	D12	I/O	1
									C	PWMH3	O	1
									D	QSPI1_IO0	I/O	2
									F	GRXCK	I	3
B8	E5	C7	VDDIOP0	GPIO_IO	PB8	I/O	–	–	A	TCLK3	I	1	PIO, I, PU, ST
									B	D13	I/O	1
									C	PWML3	O	1
									D	QSPI1_IO1	I/O	2
									F	GCRS	I	3
B6	C6	C9	VDDIOP0	GPIO_IO	PB9	I/O	–	–	A	TIOA3	I/O	1	PIO, I, PU, ST
									B	D14	I/O	1
									C	PWMFI1	I	1
									D	QSPI1_IO2	I/O	2
									F	GCOL	I	3
G6	A8	F6	VDDIOP0	GPIO_IO	PB10	I/O	–	–	A	TIOB3	I/O	1	PIO, I, PU, ST
									B	D15	I/O	1
									C	PWMEXTRG2	I	1
									D	QSPI1_IO3	I/O	2
									F	GRX2	I	3
B5	A7	B9	VDDIOP0	GPIO	PB11	I/O	–	–	A	LCDDAT0	O	1	PIO, I, PU, ST
									B	A0/NBS0	O	1
									C	URXD3	I	3
									D	PDMIC_DAT		2
									F	GRX3	I	3
A6	B6	B8	VDDIOP0	GPIO	PB12	I/O	–	–	A	LCDDAT1	O	1	PIO, I, PU, ST
									B	A1	O	1
									C	UTXD3	O	3
									D	PDMIC_CLK		2
									F	GTX2	O	3
C4	C5	B7	VDDIOP0	GPIO	PB13	I/O	–	–	A	LCDDAT2	O	1	PIO, I, PU, ST
									B	A2	O	1
									C	PCK1	O	3
									F	GTX3	O	3
G4	A6	G6	VDDIOP0	GPIO_QSPI	PB14	I/O	–	–	A	LCDDAT3	O	1	PIO, I, PU, ST
									B	A3	O	1
									C	TK1	I/O	2
									D	I2SC1_MCK	O	1
									E	QSPI1_SCK	O	3
									F	GTXCK	I/O	3
H4	E4	B5	VDDIOP0	GPIO	PB15	I/O	–	–	A	LCDDAT4	O	1	PIO, I, PU, ST
									B	A4	O	1
									C	TF1	I/O	2
									D	I2SC1_CK	I/O	1
									E	QSPI1_CS	O	3
									F	GTXEN	O	3
A4	B5	C4	VDDIOP0	GPIO_IO	PB16	I/O	–	–	A	LCDDAT5	O	1	PIO, I, PU, ST
									B	A5	O	1
									C	TD1	O	2
									D	I2SC1_WS	I/O	1
									E	QSPI1_IO0	I/O	3
									F	GRXDV	I	3
B3	C4	A5	VDDIOP0	GPIO_IO	PB17	I/O	–	–	A	LCDDAT6	O	1	PIO, I, PU, ST
									B	A6	O	1
									C	RD1	I	2
									D	I2SC1_DI0	I	1
									E	QSPI1_IO1	I/O	3
									F	GRXER	I	3
D3	A5	B4	VDDIOP0	GPIO_IO	PB18	I/O	–	–	A	LCDDAT7	O	1	PIO, I, PU, ST
									B	A7	O	1
									C	RK1	I/O	2
									D	I2SC1_DO0	O	1
									E	QSPI1_IO2	I/O	3
									F	GRX0	I	3
F4	B4	A6	VDDIOP0	GPIO_IO	PB19	I/O	–	–	A	LCDDAT8	O	1	PIO, I, PU, ST
									B	A8	O	1
									C	RF1	I/O	2
									D	TIOA3	I/O	2
									E	QSPI1_IO3	I/O	3
									F	GRX1	I	3
F2	A4	A4	VDDIOP0	GPIO	PB20	I/O	–	–	A	LCDDAT9	O	1	PIO, I, PU, ST
									B	A9	O	1
									C	TK0	I/O	1
									D	TIOB3	I/O	2
									E	PCK1	O	4
									F	GTX0	O	3
F3	D3	A3	VDDIOP0	GPIO	PB21	I/O	–	–	A	LCDDAT10	O	1	PIO, I, PU, ST
									B	A10	O	1
									C	TF0	I/O	1
									D	TCLK3	I	2
									E	FLEXCOM3_IO2	I/O	3
									F	GTX1	O	3
E4	C3	D3	VDDIOP0	GPIO	PB22	I/O	–	–	A	LCDDAT11	O	1	PIO, I, PU, ST
									B	A11	O	1
									C	TD0	O	1
									D	TIOA2	I/O	2
									E	FLEXCOM3_IO1	I/O	3
									F	GMDC	O	3
H2	B3	B2	VDDIOP0	GPIO	PB23	I/O	–	–	A	LCDDAT12	O	1	PIO, I, PU, ST
									B	A12	O	1
									C	RD0	I	1
									D	TIOB2	I/O	2
									E	FLEXCOM3_IO0	I/O	3
									F	GMDIO	I/O	3
A3	E2	E3	VDDIOP0	GPIO	PB24	I/O	–	–	A	LCDDAT13	O	1	PIO, I, PU, ST
									B	A13	O	1
									C	RK0	I/O	1
									D	TCLK2	I	2
									E	FLEXCOM3_IO3	O	3
									F	ISC_D10	I	3
H1	A3	E2	VDDIOP0	GPIO	PB25	I/O	–	–	A	LCDDAT14	O	1	PIO, I, PU, ST
									B	A14	O	1
									C	RF0	I/O	1
									E	FLEXCOM3_IO4	O	3
									F	ISC_D11	I	3
G2	G3	D4	VDDIOP0	GPIO	PB26	I/O	–	–	A	LCDDAT15	O	1	PIO, I, PU, ST
									B	A15	O	1
									C	URXD0	I	1
									D	PDMIC_DAT		1
									F	ISC_D0	I	3
H5	F4	C3	VDDIOP0	GPIO	PB27	I/O	–	–	A	LCDDAT16	O	1	PIO, I, PU, ST
									B	A16	O	1
									C	UTXD0	O	1
									D	PDMIC_CLK		1
									F	ISC_D1	I	3
J2	D2	D2	VDDIOP0	GPIO	PB28	I/O	–	–	A	LCDDAT17	O	1	PIO, I, PU, ST
									B	A17	O	1
									C	FLEXCOM0_IO0	I/O	1
									D	TIOA5	I/O	2
									F	ISC_D2	I	3
J3	G8	B3	VDDIOP0	GPIO	PB29	I/O	–	–	A	LCDDAT18	O	1	PIO, I, PU, ST
									B	A18	O	1
									C	FLEXCOM0_IO1	I/O	1
									D	TIOB5	I/O	2
									F	ISC_D3	I	3
A2	C2	F3	VDDIOP0	GPIO	PB30	I/O	–	–	A	LCDDAT19	O	1	PIO, I, PU, ST
									B	A19	O	1
									C	FLEXCOM0_IO2	I/O	1
									D	TCLK5	I	2
									F	ISC_D4	I	3
J4	G7	A2	VDDIOP0	GPIO	PB31	I/O	–	–	A	LCDDAT20	O	1	PIO, I, PU, ST
									B	A20	O	1
									C	FLEXCOM0_IO3	O	1
									D	TWD0	I/O	1
									F	ISC_D5	I	3
T14	N10	L13	VDDIOP1	GPIO	PC0	I/O	–	–	A	LCDDAT21	O	1	PIO, I, PU, ST
									B	A23	O	1
									C	FLEXCOM0_IO4	O	1
									D	TWCK0	I/O	1
									F	ISC_D6	I	3
R16	N11	H11	VDDIOP1	GPIO	PC1	I/O	–	–	A	LCDDAT22	O	1	PIO, I, PU, ST
									B	A24	O	1
									C	CANTX0	O	1
									D	SPI1_SPCK	I/O	1
									E	I2SC0_CK	I/O	1
									F	ISC_D7	I	3
T15	N9	L11	VDDIOP1	GPIO	PC2	I/O	–	–	A	LCDDAT23	O	1	PIO, I, PU, ST
									B	A25	O	1
									C	CANRX0	I	1
									D	SPI1_MOSI	I/O	1
									E	I2SC0_MCK	O	1
									F	ISC_D8	I	3
T13	M10	F13	VDDIOP1	GPIO	PC3	I/O	–	–	A	LCDPWM	O	1	PIO, I, PU, ST
									B	NWAIT	I	1
									C	TIOA1	I/O	1
									D	SPI1_MISO	I/O	1
									E	I2SC0_WS	I/O	1
									F	ISC_D9	I	3
P16	N15	G14	VDDIOP1	GPIO	PC4	I/O	–	–	A	LCDDISP	O	1	PIO, I, PU, ST
									B	NWR1/NBS1	O	1
									C	TIOB1	I/O	1
									D	SPI1_NPCS0	I/O	1
									E	I2SC0_DI0	I	1
									F	ISC_PCK	I	3
L19	M16	J14	VDDIOP1	GPIO	PC5	I/O	–	–	A	LCDVSYNC	O	1	PIO, I, PU, ST
									B	NCS0	O	1
									C	TCLK1	I	1
									D	SPI1_NPCS1	O	1
									E	I2SC0_DO0	O	1
									F	ISC_VSYNC	I	3
R15	L11	J13	VDDIOP1	GPIO	PC6	I/O	–	–	A	LCDHSYNC	O	1	PIO, I, PU, ST
									B	NCS1	O	1
									C	TWD1	I/O	1
									D	SPI1_NPCS2	O	1
									F	ISC_HSYNC	I	3
N15	M15	F14	VDDIOP1	GPIO_CLK	PC7	I/O	–	–	A	LCDPCK	O	1	PIO, I, PU, ST
									B	NCS2	O	1
									C	TWCK1	I/O	1
									D	SPI1_NPCS3	O	1
									E	URXD1	I	2
									F	ISC_MCK	O	3
P11	M13	K13	VDDIOP1	GPIO	PC8	I/O	–	–	A	LCDDEN	O	1	PIO, I, PU, ST
									B	NANDRDY	I	1
									C	FIQ	I	1
									D	PCK0	O	3
									E	UTXD1	O	2
									F	ISC_FIELD	I	3
B2	B2	–	VDDISC	GPIO	PC9	I/O	–	–	A	FIQ	I	3	PIO, I, PU, ST
									B	GTSUCOMP	O	1
									C	ISC_D0	I	1
									D	TIOA4	I/O	2
K5	G4	–	VDDISC	GPIO	PC10	I/O	–	–	A	LCDDAT2	O	2	PIO, I, PU, ST
									B	GTXCK	I/O	1
									C	ISC_D1	I	1
									D	TIOB4	I/O	2
									E	CANTX0	O	2
C2	A2	–	VDDISC	GPIO	PC11	I/O	–	–	A	LCDDAT3	O	2	PIO, I, PU, ST
									B	GTXEN	O	1
									C	ISC_D2	I	1
									D	TCLK4	I	2
									E	CANRX0	I	2
									F	A0/NBS0	O	2
D2	A1	–	VDDISC	GPIO	PC12	I/O	–	–	A	LCDDAT4	O	2	PIO, I, PU, ST
									B	GRXDV	I	1
									C	ISC_D3	I	1
									D	URXD3	I	1
									E	TK0	I/O	2
									F	A1	O	2
K2	B1	–	VDDISC	GPIO	PC13	I/O	–	–	A	LCDDAT5	O	2	PIO, I, PU, ST
									B	GRXER	I	1
									C	ISC_D4	I	1
									D	UTXD3	O	1
									E	TF0	I/O	2
									F	A2	O	2
K6	G5	–	VDDISC	GPIO	PC14	I/O	–	–	A	LCDDAT6	O	2	PIO, I, PU, ST
									B	GRX0	I	1
									C	ISC_D5	I	1
									E	TD0	O	2
									F	A3	O	2
B1	G2	–	VDDISC	GPIO	PC15	I/O	–	–	A	LCDDAT7	O	2	PIO, I, PU, ST
									B	GRX1	I	1
									C	ISC_D6	I	1
									E	RD0	I	2
									F	A4	O	2
K9	G6	–	VDDISC	GPIO	PC16	I/O	–	–	A	LCDDAT10	O	2	PIO, I, PU, ST
									B	GTX0	O	1
									C	ISC_D7	I	1
									E	RK0	I/O	2
									F	A5	O	2
C1	C1	–	VDDISC	GPIO	PC17	I/O	–	–	A	LCDDAT11	O	2	PIO, I, PU, ST
									B	GTX1	O	1
									C	ISC_D8	I	1
									E	RF0	I/O	2
									F	A6	O	2
L9	G9	–	VDDISC	GPIO	PC18	I/O	–	–	A	LCDDAT12	O	2	PIO, I, PU, ST
									B	GMDC	O	1
									C	ISC_D9	I	1
									E	FLEXCOM3_IO2	I/O	2
									F	A7	O	2
D1	D1	–	VDDISC	GPIO	PC19	I/O	–	–	A	LCDDAT13	O	2	PIO, I, PU, ST
									B	GMDIO	I/O	1
									C	ISC_D10	I	1
									E	FLEXCOM3_IO1	I/O	2
									F	A8	O	2
L8	H4	–	VDDISC	GPIO	PC20	I/O	–	–	A	LCDDAT14	O	2	PIO, I, PU, ST
									B	GRXCK	I	1
									C	ISC_D11	I	1
									E	FLEXCOM3_IO0	I/O	2
									F	A9	O	2
E3	E1	–	VDDISC	GPIO	PC21	I/O	–	–	A	LCDDAT15	O	2	PIO, I, PU, ST
									B	GTXER	O	1
									C	ISC_PCK	I	1
									E	FLEXCOM3_IO3	O	2
									F	A10	O	2
E2	F1	–	VDDISC	GPIO	PC22	I/O	–	–	A	LCDDAT18	O	2	PIO, I, PU, ST
									B	GCRS	I	1
									C	ISC_VSYNC	I	1
									E	FLEXCOM3_IO4	O	2
									F	A11	O	2
L7	H9	–	VDDISC	GPIO	PC23	I/O	–	–	A	LCDDAT19	O	2	PIO, I, PU, ST
									B	GCOL	I	1
									C	ISC_HSYNC	I	1
									F	A12	O	2
E1	G1	–	VDDISC	GPIO_CLK	PC24	I/O	–	–	A	LCDDAT20	O	2	PIO, I, PU, ST
									B	GRX2	I	1
									C	ISC_MCK	O	1
									F	A13	O	2
L4	H8	–	VDDISC	GPIO	PC25	I/O	–	–	A	LCDDAT21	O	2	PIO, I, PU, ST
									B	GRX3	I	1
									C	ISC_FIELD	I	1
									F	A14	O	2
D6	F7	–	VDDIOP2	GPIO	PC26	I/O	–	–	A	LCDDAT22	O	2	PIO, I, PU, ST
									B	GTX2	O	1
									D	CANTX1	O	1
									F	A15	O	2
E7	B10	–	VDDIOP2	GPIO	PC27	I/O	–	–	A	LCDDAT23	O	2	PIO, I, PU, ST
									B	GTX3	O	1
									C	PCK1	O	2
									D	CANRX1	I	1
									E	TWD0	I/O	2
									F	A16	O	2
J5	F6	–	VDDIOP2	GPIO	PC28	I/O	–	–	A	LCDPWM	O	2	PIO, I, PU, ST
									B	FLEXCOM4_IO0	I/O	1
									C	PCK2	O	1
									E	TWCK0	I/O	2
									F	A17	O	2
C6	B9	–	VDDIOP2	GPIO	PC29	I/O	–	–	A	LCDDISP	O	2	PIO, I, PU, ST
									B	FLEXCOM4_IO1	I/O	1
									F	A18	O	2
D7	E6	–	VDDIOP2	GPIO	PC30	I/O	–	–	A	LCDVSYNC	O	2	PIO, I, PU, ST
									B	FLEXCOM4_IO2	I/O	1
									F	A19	O	2
C8	A11	–	VDDIOP2	GPIO	PC31	I/O	–	–	A	LCDHSYNC	O	2	PIO, I, PU, ST
									B	FLEXCOM4_IO3	O	1
									C	URXD3	I	2
									F	A20	O	2
J7	E7	–	VDDIOP2	GPIO_CLK	PD0	I/O	–	–	A	LCDPCK	O	2	PIO, I, PU, ST
									B	FLEXCOM4_IO4	O	1
									C	UTXD3	O	2
									D	GTSUCOMP	O	2
									F	A23	O	2
D8	C9	–	VDDIOP2	GPIO	PD1	I/O	–	–	A	LCDDEN	O	2	PIO, I, PU, ST
									D	GRXCK	I	2
									F	A24	O	2
J6	D8	–	VDDIOP2	GPIO_CLK	PD2	I/O	–	–	A	URXD1	I	1	PIO, I, PU, ST
									D	GTXER	O	2
									E	ISC_MCK	O	2
									F	A25	O	2
M3	J1	–	VDDANA	GPIO_AD	PD3	I/O	PTC_X0	–	A	UTXD1	O	1	PIO, I, PU, ST
									B	FIQ	I	2
									D	GCRS	I	2
									E	ISC_D11	I	2
									F	NWAIT	I	2
L6	H7	–	VDDANA	GPIO_AD	PD4	I/O	PTC_X1	–	A	TWD1	I/O	2	PIO, I, PU, ST
									B	URXD2	I	1
									D	GCOL	I	2
									E	ISC_D10	I	2
									F	NCS0	O	2
L2	H1	–	VDDANA	GPIO_AD	PD5	I/O	PTC_X2	–	A	TWCK1	I/O	2	PIO, I, PU, ST
									B	UTXD2	O	1
									D	GRX2	I	2
									E	ISC_D9	I	2
									F	NCS1	O	2
J1	J2	–	VDDANA	GPIO_AD	PD6	I/O	PTC_X3	–	A	TCK	I	2	PIO, I, PU, ST
									B	PCK1	O	1
									D	GRX3	I	2
									E	ISC_D8	I	2
									F	NCS2	O	2
L5	H6	H5	VDDANA	GPIO_AD	PD7	I/O	PTC_X4	–	A	TDI	I	2	PIO, I, PU, ST
									C	UTMI_RXVAL	O	1
									D	GTX2	O	2
									E	ISC_D0	I	2
									F	NWR1/NBS1	O	2
K1	K3	J2	VDDANA	GPIO_AD	PD8	I/O	PTC_X5	–	A	TDO	O	2	PIO, I, PU, ST
									C	UTMI_RXERR	O	1
									D	GTX3	O	2
									E	ISC_D1	I	2
									F	NANDRDY	I	2
L3	J4	G4	VDDANA	GPIO_AD	PD9	I/O	PTC_X6	–	A	TMS	I	2	PIO, I, PU, ST
									C	UTMI_RXACT	O	1
									D	GTXCK	I/O	2
									E	ISC_D2	I	2
L1	J3	C2	VDDANA	GPIO_AD	PD10	I/O	PTC_X7	–	A	NTRST	I	2	PIO, I, PU, ST
									C	UTMI_HDIS	O	1
									D	GTXEN	O	2
									E	ISC_D3	I	2
N3	K2	F2	VDDANA	GPIO_AD	PD11	I/O	PTC_Y0	–	A	TIOA1	I/O	3	PIO, I, PU, ST
									B	PCK2	O	2
									C	UTMI_LS0	O	1
									D	GRXDV	I	2
									E	ISC_D4	I	2
									F	ISC_MCK	O	4
M7	K9	K4	VDDANA	GPIO_AD	PD12	I/O	PTC_Y1	–	A	TIOB1	I/O	3	PIO, I, PU, ST
									B	FLEXCOM4_IO0	I/O	2
									C	UTMI_LS1	O	1
									D	GRXER	I	2
									E	ISC_D5	I	2
									F	ISC_D4	I	4
N2	N1	C1	VDDANA	GPIO_AD	PD13	I/O	PTC_Y2	–	A	TCLK1	I	3	PIO, I, PU, ST
									B	FLEXCOM4_IO1	I/O	2
									C	UTMI_CDRCPSEL0	I	1
									D	GRX0	I	2
									E	ISC_D6	I	2
									F	ISC_D5	I	4
M6	K5	H2	VDDANA	GPIO_AD	PD14	I/O	PTC_Y3	–	A	TCK	I	1	A, PU, ST
									B	FLEXCOM4_IO2	I/O	2
									C	UTMI_CDRCPSEL1	I	1
									D	GRX1	I	2
									E	ISC_D7	I	2
									F	ISC_D6	I	4
M5	K8	G2	VDDANA	GPIO_AD	PD15	I/O	PTC_Y4	–	A	TDI	I	1	PIO, I, PU, ST
									B	FLEXCOM4_IO3	O	2
									C	UTMI_CDRCPDIVEN	I	1
									D	GTX0	O	2
									E	ISC_PCK	I	2
									F	ISC_D7	I	4
M1	L1	J1	VDDANA	GPIO_AD	PD16	I/O	PTC_Y5	–	A	TDO	O	1	PIO, I, PU, ST
									B	FLEXCOM4_IO4	O	2
									C	UTMI_CDRBISTEN	I	1
									D	GTX1	O	2
									E	ISC_VSYNC	I	2
									F	ISC_D8	I	4
M2	K1	A1	VDDANA	GPIO_AD	PD17	I/O	PTC_Y6	–	A	TMS	I	1	A, PU, ST
									C	UTMI_CDRCPSELDIV	O	1
									D	GMDC	O	2
									E	ISC_HSYNC	I	2
									F	ISC_D9	I	4
M4	J7	G3	VDDANA	GPIO_AD	PD18	I/O	PTC_Y7	–	A	NTRST	I	1	PIO, I, PU, ST
									D	GMDIO	I/O	2
									E	ISC_FIELD	I	2
									F	ISC_D10	I	4
M8	L8	K2	VDDANA	GPIO_AD	PD19	I/O	AD0	–	A	PCK0	O	1	PIO, I, PU, ST
									B	TWD1	I/O	3
									C	URXD2	I	3
									E	I2SC0_CK	I/O	2
									F	ISC_D11	I	4
N1	L2	H1	VDDANA	GPIO_AD	PD20	I/O	AD1	–	A	TIOA2	I/O	3	PIO, I, PU, ST
									B	TWCK1	I/O	3
									C	UTXD2	O	3
									E	I2SC0_MCK	O	2
									F	ISC_PCK	I	4
P3	P1	G1	VDDANA	GPIO_AD	PD21	I/O	AD2	–	A	TIOB2	I/O	3	PIO, I, PU, ST
									B	TWD0	I/O	4
									C	FLEXCOM4_IO0	I/O	3
									E	I2SC0_WS	I/O	2
									F	ISC_VSYNC	I	4
N6	L6	F1	VDDANA	GPIO_AD	PD22	I/O	AD3	–	A	TCLK2	I	3	PIO, I, PU, ST
									B	TWCK0	I/O	4
									C	FLEXCOM4_IO1	I/O	3
									E	I2SC0_DI0	I	2
									F	ISC_HSYNC	I	4
P1	T1	E1	VDDANA	GPIO_AD	PD23	I/O	AD4	–	A	URXD2	I	2	PIO, I, PU, ST
									C	FLEXCOM4_IO2	I/O	3
									E	I2SC0_DO0	O	2
									F	ISC_FIELD	I	4
N8	L4	–	VDDANA	GPIO_AD	PD24	I/O	AD5	–	A	UTXD2	O	2	PIO, I, PU, ST
N8	L4	–	VDDANA	GPIO_AD	PD24	I/O	AD5	–	C	FLEXCOM4_IO3	O	3	PIO, I, PU, ST
P8	L5	–	VDDANA	GPIO_AD	PD25	I/O	AD6	–	A	SPI1_SPCK	I/O	3	PIO, I, PU, ST
P8	L5	–	VDDANA	GPIO_AD	PD25	I/O	AD6	–	C	FLEXCOM4_IO4	O	3	PIO, I, PU, ST
P2	R1	–	VDDANA	GPIO_AD	PD26	I/O	AD7	–	A	SPI1_MOSI	I/O	3	PIO, I, PU, ST
P2	R1	–	VDDANA	GPIO_AD	PD26	I/O	AD7	–	C	FLEXCOM2_IO0	I/O	2	PIO, I, PU, ST
N5	L7	–	VDDANA	GPIO_AD	PD27	I/O	AD8	–	A	SPI1_MISO	I/O	3	PIO, I, PU, ST
									B	TCK	I	3
									C	FLEXCOM2_IO1	I/O	2
N4	L3	–	VDDANA	GPIO_AD	PD28	I/O	AD9	–	A	SPI1_NPCS0	I/O	3	PIO, I, PU, ST
									B	TDI	I	3
									C	FLEXCOM2_IO2	I/O	2
R2	M2	–	VDDANA	GPIO_AD	PD29	I/O	AD10	–	A	SPI1_NPCS1	O	3	PIO, I, PU, ST
									B	TDO	O	3
									C	FLEXCOM2_IO3	O	2
									D	TIOA3	I/O	3
									E	TWD0	I/O	3
N10	M9	–	VDDANA	GPIO_AD	PD30	I/O	AD11	–	A	SPI1_NPCS2	O	3	PIO, I, PU, ST
									B	TMS	I	3
									C	FLEXCOM2_IO4	O	2
									D	TIOB3	I/O	3
									E	TWCK0	I/O	3
P7	M8	–	VDDANA	GPIO	PD31	I/O	–	–	A	ADTRG	I	1	PIO, I, PU, ST
									B	NTRST	I	3
									C	IRQ	I	4
									D	TCLK3	I	3
									E	PCK0	O	2
M9	L9	L1	VDDANA	–	ADVREF	I	–	–	–	–	–	–	–
G1, H6	K4, J5	K3, L2	VDDANA	power	VDDANA	I	–	–	–	–	–	–	–
F1, G5	J6, M1	L3, K1	GNDANA	ground	GNDANA	I	–	–	–	–	–	–	–
M12, J10	J10, F11	K12, F12	VDDIODDR	DDR	DDR_VREF	I	–	–	–	–	–	–	–
C19	-	-	VDDIODDR	DDR	ZQ	-	-	-	-	-	-	-	-
E11, E8, H10, J13, J8, L10, P12	L10, L14, J8, H10, G12, E11, E8	F10, E8, E9, E10, G12, H12, J12	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
E10, F8, G10, J9, L11, M13, N12	K10, M14, J9, G10, H12, E10, F8	K11, J11, F9, C10, E11, F8, F11, G13, H13	GNDIODDR	ground	GNDIODDR	I	–	–	–	–	–	–	–
C3, C9, K3, U9, V5, W6, K8	H2, U3, P7, L12, E9, D7	G7, H4, D14, E14, L5	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
A1, D9, J11, K4, K7, V9, W1	E12, F12, J11, K11, K6, K7	G11, E12, E13, H3, H7, H8, J3	GNDCORE	ground	GNDCORE	I	–	–	–	–	–	–	–
B4, D5	D4, F3	F4, E4	VDDIOP0	power	VDDIOP0	I	–	–	–	–	–	–	–
A5, D4	E3, F2	E5, F5	GNDIOP0	ground	GNDIOP0	I	–	–	–	–	–	–	–
V13, V18	N12, P12	N9, N10	VDDIOP1	power	VDDIOP1	I	–	–	–	–	–	–	–
P13, R13, W13, W19	M12, P11	M9, M10	GNDIOP1	ground	GNDIOP1	I	–	–	–	–	–	–	–
A8	D9	–	VDDIOP2	power	VDDIOP2	I	–	–	–	–	–	–	–
B9	D6	–	GNDIOP2	ground	GNDIOP2	I	–	–	–	–	–	–	–
T7	N8	J7	VDDSDMMC	power	VDDSDMMC	I	–	–	–	–	–	–	–
T8	R8	J8	GNDSDMMC	ground	GNDSDMMC	I	–	–	–	–	–	–	–
G3	H3	–	VDDISC	power	VDDISC	I	–	–	–	–	–	–	–
H3	H5	–	GNDISC	ground	GNDISC	I	–	–	–	–	–	–	–
U15	N13	M13	VDDFUSE	power	VDDFUSE	I	–	–	–	–	–	–	–
P9	R5	P4	VDDPLLA	power	VDDPLLA	I	–	–	–	–	–	–	–
P10	T5	L6	GNDPLLA	ground	GNDPLLA	I	–	–	–	–	–	–	–
R6	M4	K6	VDDAUDIOPLL	power	VDDAUDIOPLL	I	–	–	–	–	–	–	–
N9	T3	J6	GNDDPLL	ground	GNDDPLL	I	–	–	–	–	–	–	–
P6	T4	H6	GNDAUDIOPLL	ground	GNDAUDIOPLL	I	–	–	–	–	–	–	–
W2	T8	P1	VDDAUDIOPLL	–	CLK_AUDIO	O	–	–	–	–	–	–	–
W5	U9	N5	VDDOSC	–	XIN	I	–	–	–	–	–	–	–
W4	U8	P5	VDDOSC	–	XOUT	O	–	–	–	–	–	–	–
R10	N6	M7	VDDOSC	–	VDDOSC	I	–	–	–	–	–	–	–
T11	P5	N6	GNDOSC	ground	GNDOSC	I	–	–	–	–	–	–	–
R8	P6	M6	VDDUTMII	power	VDDUTMII	I	–	–	–	–	–	–	–
U7	R7	–	VDDHSIC	power	VDDHSIC	I	–	–	–	–	–	–	–
R7	M6	L7	GNDUTMII	ground	GNDUTMII	I	–	–	–	–	–	–	–
W7	U10	N7	VDDUTMII	–	HHSDPA	I/O	–	–	–	–	–	–	–
V7	T10	P7	VDDUTMII	–	HHSDMA	I/O	–	–	–	–	–	–	–
W8	U11	N8	VDDUTMII	–	HHSDPB	I/O	–	–	–	–	–	–	–
V8	T11	P8	VDDUTMII	–	HHSDMB	I/O	–	–	–	–	–	–	–
W9	T12	–	VDDHSIC	–	HHSDPDATC	I/O	–	–	–	–	–	–	–
W10	U12	–	VDDHSIC	–	HHSDMSTRC	I/O	–	–	–	–	–	–	–
T6	M7	K7	VDDUTMIC	power	VDDUTMIC	I	–	–	–	–	–	–	–
U6	R6	G5	GNDUTMIC	ground	GNDUTMIC	I	–	–	–	–	–	–	–
V6	T6	P6	VDDUTMIC	–	VBG	I	–	–	–	–	–	–	–
T2	R4	D1	VDDBU	–	TST	I	–	–	–	–	–	–	–
W3	T7	J5	VDDBU	–	NRST	I	–	–	–	–	–	–	–
T3	R3	N3	VDDBU	–	JTAGSEL	I	–	–	–	–	–	–	–
U2	R2	N1	VDDBU	–	WKUP	I	–	–	–	–	–	–	–
R1	N2	–	VDDBU	–	RXD	I	–	–	–	–	–	–	–
P4	T2	B1	VDDBU	–	SHDN	O	–	–	–	–	–	–	–
R4	P3	N4	VDDBU	–	PIOBU0	I/O	–	–	–	–	–	–	–
R5	M3	L4	VDDBU	–	PIOBU1	I/O	–	–	–	–	–	–	–
R3	P2	M3	VDDBU	–	PIOBU2	I/O	–	–	–	–	–	–	–
T4	P4	M4	VDDBU	–	PIOBU3	I/O	–	–	–	–	–	–	–
U3	N4	J4	VDDBU	–	PIOBU4	I/O	–	–	–	–	–	–	–
T5	M5	M5	VDDBU	–	PIOBU5	I/O	–	–	–	–	–	–	–
U5	N5	–	VDDBU	–	PIOBU6	I/O	–	–	–	–	–	–	–
P5	N3	–	VDDBU	–	PIOBU7	I/O	–	–	–	–	–	–	–
V3	U5	K5	VDDBU	power	VDDBU	I	–	–	–	–	–	–	–
U4	U4	N2	GNDBU	ground	GNDBU	I	–	–	–	–	–	–	–
U1	U2	M1	VDDBU	–	XIN32	I	–	–	–	–	–	–	–
T1	U1	M2	VDDBU	–	XOUT32	O	–	–	–	–	–	–	–
V1	U6	P2	VDDBU	–	COMPP	I	–	–	–	–	–	–	–
V2	U7	P3	VDDBU	–	COMPN	I	–	–	–	–	–	–	–
-	D17	D12	DDRM_VDDQ⁽²⁾	–	ODT	I	–	–	–	–	–	–	–
-	A16, B16, C16, D16, E15, G17, J17, L16	B10, A12, D10, D11	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
-	E16	E7	DDRM_VDDL⁽²⁾	power	DDRM_VDDL⁽²⁾	I	–	–	–	–	–	–	–
-	F15, G15, H15, J15, K15, L15	A7, A13, A9, A11, B6, C12	DDRM_VDDQ⁽²⁾	power	DDRM_VDDQ⁽²⁾	–	–	–	–	–	–	–	–
A14, A19, B14, B18, C14, C18, D14, D18, E14, E18, F14, F18, G14, G18, H14, H18, N14, N17, N18, P14, P18, R14, R18, T18	A17, B17, C17, D15, E14, F17, H17, L17	B14, A8, C11, C14, D8	DDRM_VSS	ground	DDRM_VSS	–	–	–	–	–	–	–	–
-	E17	D13	DDRM_VSSDL	ground	DDRM_VSSDL	I	–	–	–	–	–	–	–
-	F16, G16, H16, J16, K16, K17	A10, A14, B11, B12, B13, C13	DDRM_VSSQ	ground	DDRM_VSSQ	I	–	–	–	–	–	–	–
B15, B17, B19, D15, D17, D19, F15, F17, F19, H15, H17, H19, K15, K17, K19, M15, M17, M19, P15, P17, P19, T17, T19	-	-	DDRM_VDD12⁽³⁾	power	DDRM_VDD12⁽³⁾	I	-	-	-	-	-	-	-
B11, B13, D11, D13, K13, K16	-	-	DDRM_VDD18⁽³⁾	power	DDRM_VDD18⁽³⁾	I	-	-	-	-	-	-	-
A13, A15, A16, A17, A18, B10, B12, B16, C10, C11, C12, C13, C15, C16, C17, D10, D12, D16, E12, E13, E15, E16, E17, E19, E5, E6, E9, F10, F11, F12, F13, F16, F5, F6, F7, F9, G11, G12, G13, G15, G16, G17, G19, G7, G8, G9, H11, H12, H13, H16, H7, H8, H9, J12, J14, J15, J16, J17, J18, J19, K10, K11, K12, K14, L12, L13, L14, L15, L16, M10, M11, M14, N11, N13, N16, N7, R11, R12, R17, T12, T9, U10, U11, U8, V4	A12, A13, A14, A15, B11, B12, B13, B14, B15, C10, C11, C12, C13, C14, C15, D10, D11, D12, D13, D14, E13, F9, F10, F13, F14, G11, G13, G14, H11, H13, H14, J12, J13, J14, K12, K13, K14, L13, R12, T9	–	–	NC⁽⁴⁾	–	–	–	–	–	–	–	–	–

Note:

Signal = ‘PIO’ if GPIO; Dir = Direction; PU = Pull-up; PD = Pull-down; HiZ = High impedance; ST = Schmitt Trigger
Refer to the DDR2-SDRAM data sheet for DDRM_VDDQ and DDRM_VDDL definitions. DDRM_VDDQ/DDRM_VDDL = 1.8V ±0.1V.
DDRM_VDD18 stands for VDD1, DDRM_VDD12 stands for VDD2, refer to the LPDDR2-SDRAM data sheet for VDD1 and VDD2 definitions.
These balls are not internally connected, they can be left unconnected, connected to any GND, VDD or to any slowly varying signal to avoid any EMI related issues.