4.4 Processor (CPU_CLK) and main system bus clock (MCK) source selection
When changing the fields CSS or CPCSS in the CPU Clock register (PMC_CPU_CKR) from any PLL source clocks (PLLxCKx) to Slow Clock source (SLOW_CLK), the clock switching circuitry first switches from the PLL source to MAINCK source, then to Slow Clock source.
There is no impact on the clock switching sequence or device behavior. This intermediate step can be observed when the main system bus clock is output on a PCK pin.
Work Around
None
Affected Silicon Revisions
|
A0 A0-D1G A0-D2G |
A1 A1-D1G A1-D2G A1-D5M | ||||||
| X | X |