3.1 LCDC Register Write Protection status incorrect on some registers
WPVS bit does not rise when a write protect violation occurs on the following registers:
LCDC_HEOVTAP10Px [x=0..15]
LCDC_HEOVTAP32Px [x=0..15]
LCDC_HEOHTAP10Px [x=0..15]
LCDC_HEOHTAP32Px [x=0..15]
Note the protection is effective even if the status bit does not rise.
Work Around
None
Affected Device Revisions
|
A0 A0-D1G A0-D2G |
A1 A1-D1G A1-D2G A1-D5M | ||||||
| X | X |