11.4 Register Summary
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | MCLKCTRLA | 7:0 | CLKOUT | CLKSEL[3:0] | ||||||
| 0x01 | MCLKCTRLB | 7:0 | PDIV[3:0] | PEN | ||||||
| 0x02 | MCLKLOCK | 7:0 | LOCKEN | |||||||
| 0x03 | MCLKSTATUS | 7:0 | PLLS | EXTS | XOSC32KS | OSC32KS | OSCHFS | SOSC | ||
0x04 ... 0x07 | Reserved | |||||||||
| 0x08 | OSCHFCTRLA | 7:0 | RUNSTDBY | FRQSEL[3:0] | AUTOTUNE | |||||
| 0x09 | OSCHFTUNE | 7:0 | TUNE[7:0] | |||||||
0x0A ... 0x0F | Reserved | |||||||||
| 0x10 | PLLCTRLA | 7:0 | RUNSTDBY | SOURCE | MULFAC[1:0] | |||||
0x11 ... 0x17 | Reserved | |||||||||
| 0x18 | OSC32KCTRLA | 7:0 | RUNSTDBY | |||||||
0x19 ... 0x1B | Reserved | |||||||||
| 0x1C | XOSC32KCTRLA | 7:0 | RUNSTDBY | CSUT[1:0] | SEL | LPMODE | ENABLE | |||