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AVR® DA Family

AVR128DA28 AVR128DA32 AVR128DA48 AVR128DA64

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40 Package Drawings
40.10 48-Pin VQFN Wettable Flanks

Introduction
AVR® DA Family Overview
Features
1 Block Diagram
2 Pinout
3 I/O Multiplexing and Considerations
4 Hardware Guidelines
5 Conventions
6 AVR® CPU
7 Memories
8 Peripherals and Architecture
9 GPR - General Purpose Registers
10 NVMCTRL - Nonvolatile Memory Controller
11 CLKCTRL - Clock Controller
12 SLPCTRL - Sleep Controller
13 RSTCTRL - Reset Controller
14 CPUINT - CPU Interrupt Controller
15 EVSYS - Event System
16 PORTMUX - Port Multiplexer
17 PORT - I/O Pin Configuration
18 BOD - Brown-out Detector
19 VREF - Voltage Reference
20 WDT - Watchdog Timer
21 TCA - 16-bit Timer/Counter Type A
22 TCB - 16-Bit Timer/Counter Type B
23 TCD - 12-Bit Timer/Counter Type D
24 RTC - Real-Time Counter
25 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
26 SPI - Serial Peripheral Interface
27 TWI - Two-Wire Interface
28 CRCSCAN - Cyclic Redundancy Check Memory Scan
29 CCL - Configurable Custom Logic
30 AC - Analog Comparator
31 ADC - Analog-to-Digital Converter
32 DAC - Digital-to-Analog Converter
33 PTC - Peripheral Touch Controller
34 ZCD - Zero-Cross Detector
35 UPDI - Unified Program and Debug Interface
36 Instruction Set Summary
37 Electrical Characteristics
38 Characteristics Graphs
39 Ordering Information
40 Package Drawings
41 Data Sheet Revision History
Microchip Information

40.10 48-Pin VQFN Wettable Flanks

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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