3.1 I/O Multiplexing


VQFN64/ TQFP64	VQFN48/ TQFP48	VQFN32/ TQFP32	SPDIP28/ SOIC28/ SSOP28	Pin name ^(1,2)	Special	ADC0	PTC	ACn	DAC0	ZCDn	USARTn	SPIn	TWIn⁽⁴⁾	TCA0	TCA1	TCBn	TCDn	EVSYS	CCL-LUTn
62	44	30	22	PA0	EXTCLK		XO/Y0				0,TxD			WO0					0,IN0
63	45	31	23	PA1			X1/Y1				0,RxD			WO1					0,IN1
64	46	32	24	PA2	TWI		X2/Y2				0,XCK		0,SDA(H)	WO2		0,WO		EVOUTA	0,IN2
1	47	1	25	PA3	TWI		X3/Y3				0,XDIR		0,SCL(H)	WO3		1,WO			0,OUT
2	48	2	26	PA4			X4/Y4				0,TxD⁽³⁾	0,MOSI		WO4			0,WOA
3	1	3	27	PA5			X5/Y5				0,RxD⁽³⁾	0,MISO		WO5			0,WOB
4	2	4	28	PA6			X6/Y6				0,XCK⁽³⁾	0,SCK					0,WOC		0,OUT⁽³⁾
5	3	5	1	PA7	CLKOUT		X7/Y7	0,OUT 1,OUT 2,OUT		0,OUT 1,OUT 2,OUT	0,XDIR⁽³⁾	0,SS					0,WOD	EVOUTA ⁽³⁾
6				VDD
7				GND
8	4			PB0			X8/Y8				3,TxD			WO0⁽³⁾	WO0				4,IN0
9	5			PB1			X9/Y9				3,RxD			WO1⁽³⁾	WO1				4,IN1
10	6			PB2			X10/Y10				3,XCK		1,SDA(H)⁽³⁾	WO2⁽³⁾	WO2			EVOUTB	4,IN2
11	7			PB3			X11/Y11				3,XDIR		1,SCL(H)⁽³⁾	WO3⁽³⁾	WO3				4,OUT
12	8			PB4			X12/Y12				3,TxD⁽³⁾	1,MOSI⁽³⁾		WO4⁽³⁾	WO4	2,WO⁽³⁾	0,WOA⁽³⁾
13	9			PB5			X13/Y13				3,RxD⁽³⁾	1,MISO⁽³⁾		WO5⁽³⁾	WO5	3,WO	0,WOB⁽³⁾
14				PB6			X14/Y14				3,XCK⁽³⁾	1,SCK⁽³⁾	1,SDA(C)⁽³⁾				0,WOC⁽³⁾		4,OUT⁽³⁾
15				PB7			X15/Y15				3,XDIR⁽³⁾	1,SS⁽³⁾	1,SCL(C)⁽³⁾				0,WOD⁽³⁾	EVOUTB ⁽³⁾
16	10	6	2	PC0							1,TxD	1,MOSI		WO0⁽³⁾		2,WO			1,IN0
17	11	7	3	PC1							1,RxD	1,MISO		WO1⁽³⁾		3,WO⁽³⁾			1,IN1
18	12	8	4	PC2	TWI						1,XCK	1,SCK	0,SDA(H)⁽³⁾	WO2⁽³⁾				EVOUTC	1,IN2
19	13	9	5	PC3	TWI						1,XDIR	1,SS	0,SCL(H)⁽³⁾	WO3⁽³⁾					1,OUT
20	14			VDD
21	15			GND
22	16			PC4							1,TxD⁽³⁾	1,MOSI⁽³⁾		WO4⁽³⁾	WO0⁽³⁾
23	17			PC5							1,RxD⁽³⁾	1,MISO⁽³⁾		WO5⁽³⁾	WO1⁽³⁾
24	18			PC6				0,OUT⁽³⁾ 1,OUT⁽³⁾ 2,OUT⁽³⁾			1,XCK⁽³⁾	1,SCK⁽³⁾	0,SDA(C)		WO2⁽³⁾	4,WO⁽³⁾			1,OUT⁽³⁾
25	19			PC7						0,OUT⁽³⁾ 1,OUT⁽³⁾ 2,OUT⁽³⁾	1,XDIR⁽³⁾	1,SS⁽³⁾	0,SCL(C)					EVOUTC ⁽³⁾
26	20	10	6	PD0		AIN0	X16/Y16	0,AINN1 1,AINN1 2,AINN1						WO0⁽³⁾					2,IN0
27	21	11	7	PD1		AIN1	X17/Y17			0,ZCIN				WO1⁽³⁾					2,IN1
28	22	12	8	PD2		AIN2	X18/Y18	0,AINP0 1,AINP0 2,AINP0						WO2⁽³⁾				EVOUTD	2,IN2
29	23	13	9	PD3		AIN3	X19/Y19	0,AINN0 1,AINP1						WO3⁽³⁾					2,OUT
30	24	14	10	PD4		AIN4	X20/Y20	1,AINP2 2,AINP1						WO4⁽³⁾
31	25	15	11	PD5		AIN5	X21/Y21	1,AINN0						WO5⁽³⁾
32	26	16	12	PD6		AIN6	X22/Y22	0,AINP3 1,AINP3 2,AINP3	VOUT										2,OUT⁽³⁾
33	27	17	13	PD7	VREFA	AIN7	X23/Y23	0,AINN2 1,AINN2 2,AINN0/AINN2										EVOUTD ⁽³⁾
34	28	18	14	AVDD
35	29	19	15	GND
36	30			PE0		AIN8	X24/Y24	0,AINP1			4,TxD	0,MOSI⁽³⁾		WO0⁽³⁾
37	31			PE1		AIN9	X25/Y25	2,AINP2			4,RxD	0,MISO⁽³⁾		WO1⁽³⁾
38	32			PE2		AIN10	X26/Y26	0,AINP2			4,XCK	0,SCK⁽³⁾		WO2⁽³⁾				EVOUTE
39	33			PE3		AIN11	X27/Y27			1,ZCIN	4,XDIR	0,SS⁽³⁾		WO3⁽³⁾
40				PE4		AIN12	X28/Y28				4,TxD⁽³⁾			WO4⁽³⁾	WO0⁽³⁾
41				PE5		AIN13	X29/Y29				4,RxD⁽³⁾			WO5⁽³⁾	WO1⁽³⁾
42				PE6		AIN14	X30/Y30				4,XCK⁽³⁾				WO2⁽³⁾
43				PE7		AIN15	X31/Y31			2,ZCIN	4,XDIR⁽³⁾							EVOUTE ⁽³⁾
44	34	20	16	PF0	XTAL32K1	AIN16⁽⁶⁾	X32/Y32				2,TxD			WO0⁽³⁾			0,WOA⁽³⁾		3,IN0
45	35	21	17	PF1	XTAL32K2	AIN17⁽⁶⁾	X33/Y33				2,RxD			WO1⁽³⁾			0,WOB⁽³⁾		3,IN1
46	36	22		PF2	TWI	AIN18⁽⁶⁾	X34/Y34				2,XCK		1,SDA(H)	WO2 ⁽³⁾			0,WOC ⁽³⁾	EVOUTF	3,IN2
47	37	23		PF3	TWI	AIN19⁽⁶⁾	X35/Y35				2, XDIR		1,SCL(H)	WO3 ⁽³⁾			0,WOD ⁽³⁾		3,OUT
48	38	24		PF4		AIN20⁽⁶⁾	X36/Y36				2, TxD ⁽³⁾			WO4 ⁽³⁾		0,WO ⁽³⁾
49	39	25		PF5		AIN21⁽⁶⁾	X37Y37				2, RxD ⁽³⁾			WO5⁽³⁾		1,WO⁽³⁾
50	40	26	18	PF6 ⁽⁵⁾	RESET
51	41	27	19	UPDI
52				PG0			X40/Y40				5, TxD			WO0 ⁽³⁾	WO0 ⁽³⁾				5,IN0
53				PG1			X41/Y41				5,RxD			WO1⁽³⁾	WO1⁽³⁾				5,IN1
54				PG2			X42/Y42				5,XCK			WO2⁽³⁾	WO2⁽³⁾			EVOUTG	5,IN2
55				PG3			X43/Y43				5,XDIR			WO3⁽³⁾	WO3⁽³⁾	4,WO			5,OUT
56	42	28	20	VDD
57	43	29	21	GND
58				PG4			X44/Y44				5,TxD⁽³⁾	0,MOSI⁽³⁾		WO4⁽³⁾	WO4⁽³⁾		0,WOA⁽³⁾
59				PG5			X45/Y45				5,RxD⁽³⁾	0,MISO⁽³⁾		WO5⁽³⁾	WO5⁽³⁾		0,WOB⁽³⁾
60				PG6			X46/Y46				5,XCK⁽³⁾	0,SCK⁽³⁾					0,WOC⁽³⁾		5,OUT⁽³⁾
61				PG7			X47/Y47				5,XDIR⁽³⁾	0,SS⁽³⁾					0,WOD⁽³⁾	EVOUTG ⁽³⁾

Note:

Pin names are of type Pxn, with x being the PORT instance (A, B, C, ...) and n the pin number. Notation for signals is PORTx_PINn. All pins can be used as event input.
All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous detection.
Alternate pin positions. For selecting the alternate positions, refer to the Port Multiplexer section.
The TWI pins that can be used as host or client are marked H. Pins with client only are marked C.
Input-only.
Positive input-only.