12.5.9 PLL Control A

Name: PLLCTRLA
Offset: 0x10
Reset: 0x00
Property: Configuration Change Protection

Bit 76543210 
 RUNSTDBYSOURCE    MULFAC[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 7 – RUNSTDBY Run Standby

This bit controls whether the Phase-Locked Loop (PLL) is always running or not.

Note:
  1. The requesting peripheral must take the PLL start-up time and PLL source start-up time into account.
  2. The oscillator signal will only be available if requested and will be available after two PLL cycles.

ValueDescription
0The PLL will only run if requested by a peripheral (1)
1The PLL will always run in Active, Idle and Standby sleep modes (2)

Bit 6 – SOURCE Select Source for PLL

This bit controls the Phase-Locked Loop (PLL) clock source.

ValueNameDescription
0OSCHFThe internal high-frequency oscillator as PLL source
1XOSCHFThe external high-frequency clock or the external high-frequency oscillator as PLL source

Bits 1:0 – MULFAC[1:0] Multiplication Factor

This bit field controls the multiplication factor for the Phased-Locked Loop (PLL).
ValueNameDescription
0x0DISABLEPLL is disabled
0x12x2 x multiplication factor
0x23x3 x multiplication factor
0x3-Reserved