12.5.9 PLL Control A
Name: | PLLCTRLA |
Offset: | 0x10 |
Reset: | 0x00 |
Property: | Configuration Change Protection |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
RUNSTDBY | SOURCE | MULFAC[1:0] | |||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit 7 – RUNSTDBY Run Standby
This bit controls whether the Phase-Locked Loop (PLL) is always running or not.
Note:
- The requesting peripheral must take the PLL start-up time and PLL source start-up time into account.
- The oscillator signal will only be available if requested and will be available after two PLL cycles.
Value | Description |
---|---|
0 | The PLL will only run if requested by a peripheral (1) |
1 | The PLL will always run in Active, Idle and Standby sleep modes (2) |
Bit 6 – SOURCE Select Source for PLL
This bit controls the Phase-Locked Loop (PLL) clock source.
Value | Name | Description |
---|---|---|
0 | OSCHF | The internal high-frequency oscillator as PLL source |
1 | XOSCHF | The external high-frequency clock or the external high-frequency oscillator as PLL source |
Bits 1:0 – MULFAC[1:0] Multiplication Factor
Value | Name | Description |
---|---|---|
0x0 | DISABLE | PLL is disabled |
0x1 | 2x | 2 x multiplication factor |
0x2 | 3x | 3 x multiplication factor |
0x3 | - | Reserved |