17.3.2 CCL LUTn Pin Position
| Name: | CCLROUTEA |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LUT4 | LUT3 | LUT2 | LUT1 | LUT0 | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 4 – LUT4 CCL LUT 4 Signals
This bit field controls the pin positions for CCL LUT 4 signals.
| Value | Name | Description | |||
|---|---|---|---|---|---|
| OUT | IN0 | IN1 | IN2 | ||
0 | DEFAULT | PB3 | PB0 | PB1 | PB2 |
1 | ALT1 | PB6 | PB0 | PB1 | PB2 |
Bit 3 – LUT3 CCL LUT 3 Signals
This bit field controls the pin positions for CCL LUT 3 signals.
| Value | Name | Description | |||
|---|---|---|---|---|---|
| OUT | IN0 | IN1 | IN2 | ||
0 | DEFAULT | PF3 | PF0 | PF1 | PF2 |
1 | - | Reserved | Reserved | Reserved | Reserved |
Bit 2 – LUT2 CCL LUT 2 Signals
This bit field controls the pin positions for CCL LUT 2 signals.
| Value | Name | Description | |||
|---|---|---|---|---|---|
| OUT | IN0 | IN1 | IN2 | ||
0 | DEFAULT | PD3 | PD0 | PD1 | PD2 |
1 | ALT1 | PD6 | PD0 | PD1 | PD2 |
Bit 1 – LUT1 CCL LUT 1 Signals
This bit field controls the pin positions for CCL LUT 1 signals.
| Value | Name | Description | |||
|---|---|---|---|---|---|
| OUT | IN0 | IN1 | IN2 | ||
0 | DEFAULT | PC3 | PC0 | PC1 | PC2 |
1 | ALT1 | PC6 | PC0 | PC1 | PC2 |
Bit 0 – LUT0 CCL LUT 0 Signals
This bit field controls the pin positions for CCL LUT 0 signals.
| Value | Name | Description | |||
|---|---|---|---|---|---|
| OUT | IN0 | IN1 | IN2 | ||
0 | DEFAULT | PA3 | PA0 | PA1 | PA2 |
1 | ALT1 | PA6 | PA0 | PA1 | PA2 |