24.3.3.3 32-Bit Input Capture

Two 16-bit Timer/Counter Type B (TCBn) can be combined to work as a true 32-bit input capture:

One TCB is counting the two LSBs. Once this counter reaches MAX, an overflow (OVF) event is generated, and the counter wraps around. The second TCB is configured to count these OVF events and thus provides the two MSBs. The 32-bit counter value is concatenated from the two counter values.

To function as a 32-bit counter, the two TCBs and the system have to be set up as described in the following paragraphs.

System Configuration

  • Configure a source (TCA, events, CLK_PER) for the count input for the LSB TCB, according to the application requirements
  • Configure the event system to route the OVF events from the LSB TCB (event generator) to the TCB intended for counting the MSB (event user)
  • Configure the event system to route the same capture event (CAPT) generator to both TCBs

Configuration of the LSB Counter

  • Select the configured count input by writing the Clock Select (CLKSEL) bit field in the Control A (CTRLA) register
  • Write the Timer Mode (CNTMODE) bit field in the Control B (CTRLB) register to select the Input Capture on Event mode
  • Ensure that the Cascade Two Timer/Counters (CASCADE) bit in CTRLA is ‘0’

Configuration of the MSB Counter

  • Enable the 32-bit mode by writing the Cascade Two Timer/Counters bit (CASCADE) in CTRLA to ‘1’
  • Select events as clock input by writing to the Clock Select (CLKSEL) bit field in the Control A (CTRLA) register
  • Write the Timer Mode (CNTMODE) bit field in the Control B (CTRLB) register to select the Input Capture on Event mode

Capturing a 32-Bit Counter Value

To acquire a 32-bit counter value, send a CAPT event to both TCBs. Both TCBs are running in Input Capture on Event mode, so each will capture the current counter value (CNT) in the respective Capture/Compare (CCMP) register. The 32-bit capture value is formed by concatenating the two CCMP registers.

Using TCB0 as LSB Counter and TCB1 as MSB Counter

TCB0 is counting the count input, and TCB1 is counting the OVF signals from TCB0.

A CAPT event is generated and causes both TCB0 and TCB1 to copy their current CNT values to their respective CCMP registers. The two different CASCADE bit values allow correct timing of the CAPT event.

The captured 32-bit value is concatenated from TCB1.CCMP (MSB) and TCB0.CCMP (LSB).