23.5.7 Control Register F Clear

Use this register instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit location.

Name: CTRLFCLR
Offset: 0x06
Reset: 0x00
Property: -

Bit 76543210 
     CMP2BVCMP1BVCMP0BVPERBV 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 3 – CMP2BV Compare 2 Buffer Valid

See CMP0BV.

Bit 2 – CMP1BV Compare 1 Buffer Valid

See CMP0BV.

Bit 1 – CMP0BV Compare 0 Buffer Valid

The CMPnBV bits are set when a new value is written to the corresponding TCAn.CMPnBUF register. These bits are automatically cleared on an UPDATE condition.

Bit 0 – PERBV Period Buffer Valid

This bit is set when a new value is written to the TCAn.PERBUF register. This bit is automatically cleared on an UPDATE condition.