39.4.4 I/O Pin Characteristics

Table 39-7. I/O Pin Characteristics(1)
SymbolDescriptionMin.Typ.Max.UnitsConditions
Input Low Voltage
VILI/O PORT:
  • With Schmitt Trigger buffer
——0.2×VDDV
  • With I2C levels
——0.3×VDDV
  • With SMBus 3.0 levels
——0.8V
RESET Pin——0.2×VDDV
TTL level——0.8V
Input High Voltage
VIHI/O PORT:
  • With Schmitt Trigger buffer
0.8×VDD——V
  • With I2C levels
0.7×VDD——V
  • With SMBus 3.0 levels
1.35——V
RESET Pin0.8×VDD——V
TTL level1.6——V
Input Leakage Current(2)
IILI/O PORTS(3)—<5—nAGND ≤ VPIN ≤ VDD,

pin at high-impedance, 85°C

—<5—nAGND ≤ VPIN(5) ≤ VDD,

pin at high-impedance, 125°C

RESET Pin(4)—±50—nAGND ≤ VPIN ≤ VDD,

pin at high-impedance, 85°C

Pull-up Current
IPUR—140—μAVDD = 3.0V, VPIN = GND
Output Low Voltage
VOLStandard I/O Ports——0.6VIOL = 10 mA, VDD = 3.0V
Output High Voltage
VOHStandard I/O PortsVDD-0.7——VIOH = 6 mA, VDD = 3.0V
Pin Capacitance
CIOOp amp output—9—pF
VREFpin—7—pF
XTAL pins—4—pF
Other pins—4—pF
Note:
  1. These figures are valid for all I/O ports regardless of if they are connected to the VDD or VDDIO2 power domain.
  2. The negative current is defined as current sourced by the pin.
  3. The leakage current numbers for I/O PORTS are valid also when the pin is used as an input to an enabled analog peripheral.
  4. The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
  5. A requirement for all I/O pins.