2.4 Pin Descriptions

This section contains descriptions of the various LAN8650/1 pins. The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the high voltage level.

The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of “active low” and “active high” signals. The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.

Table 2-4. Serial Peripheral Interface (SPI) Pins
Name	Symbol	Buffer Type	Description
Serial Clock	SCLK	VIS-VDDP	Serial clock input
Serial Data In	SDI	VIS-VDDP	Serial data input
Serial Data Out	SDO	VOH-VDDP	Serial data output
Serial Chip Select	CS_N	VIS-VDDP (PU)	Serial peripheral chip select
Interrupt	IRQ_N	VO-VDDP (PU)	Device interrupt (Active low) Note: In some cases, the host controllers may require a 10 kΩ (typical) pull-up to its I/O power supply.

Table 2-5. Ethernet Transceiver Pins
Name	Symbol	Buffer Type	Description
Ethernet TX/RX Positive  Terminal	TRXP	AIO	Positive terminal for transmit/receive signal
Ethernet TX/RX Negative  Terminal	TRXN	AIO	Negative terminal for transmit/receive signal

Table 2-6. Power Management Pins
Name	Symbol	Buffer Type	Description
Inhibit	INH	VODH-VDDAU	Inhibit. Used to switch on/off the main external voltage regulators. This pin operates in the VDDAU domain. RESET_N assertion does not affect the state of this pin. This signal is an active high, P-channel open-drain source output. The pin will be driven to VDDAU to inhibit the shutdown of external voltage regulators. When the external regulators may be shutdown, this pin will become high impedance. Note: When used, this pin requires a pull-down resistor. When not used, this pin should be left unconnected.
Wake Input	WAKE_IN	VI-VDDAU	Wakeup Input. Asserted to move the part out of sleep. This pin implements the optional wake input described in the TC10 specification. Note: When used, this pin requires a pull-up or pull-down resistor, depending on the software configured assertion polarity. Note: This pin operates in the VDDAU domain. When not used, this pin should be connected to VSS.
Wake Output	WAKE_OUT	VO-VDDP	Wake Output. Asserted when the part wakes out of sleep. This pin implements the optional wake output described in the TC10 specification. Note: When used, this pin requires a pull-down resistor. Note: This pin operates in the VDDP domain. When not used, this pin should be left unconnected.

Table 2-7. Configurable Pins
Name	Symbol	Buffer Type	Description
Warning: Reserved bits of the pad control register must not be written with any values other than their default without instruction from Microchip.
Configurable Pins	DIOA0 DIOA1 DIOA2 DIOA3 DIOA4 DIOB0	VIS-VDDP, VO-VDDP	These pins may be configured as input or output for various purposes. When not used, these pins may be connected directly to ground.
Reserved	DIOB1		This pin is reserved for Microchip test use. It is recommended that this pin is connected directly to ground.

Table 2-8. Miscellaneous Pins
Name	Symbol	Buffer Type	Description
External 25 MHz Crystal Input	XTI	ICLK	External 25 MHz crystal input
External 25 MHz Crystal Output	XTO	OCLK	External 25 MHz crystal output
System Reset	RESET_N	VIS-VDDP	System reset. This pin is active low. When not used, this pin may be connected directly to VDDP.
Bias  Resistor	RBIAS	AI	External bias resistor connection pin. This pin requires connection of a 12.4 kΩ resistor to ground. Note: The resistor must be within ± 1% tolerance across the entire expected operating temperature range.
Reserved for Test	TEST	VIS-VDDP	This pin should be connected to VDDP.
Do Not Connect	DNC	-	The pin must be left floating externally unless otherwise directed by Microchip.

Table 2-9. Power Pins
Name	Symbol	Description
Core LDO Supply Compensation	CCOMP	Internal +1.8V LDO core compensation Note: This pin requires a 4.7 μF low ESR capacitor to the PCB ground plane. Note: This pin is only on the LAN8651.
+1.8V Switchable Core Power Supply Input	VDDC	+1.8V core power supply input. When in sleep mode, this supply must be disabled. Note: These pins are only on the LAN8650.
+3.3V Switchable I/O Power Supply Input	VDDP	+3.3V I/O power supply input. When in sleep mode, this supply must be disabled.
+3.3V Continuous VDDAU Power  Supply Input	VDDAU	+3.3V continuous VDDAU power supply input. Note: This supply must be provided during sleep mode. Note: When wake/sleep support is not used, this pin is connected to the same supply as VDDA.
+3.3V Switchable Analog Power  Supply Input	VDDA	+3.3V analog power supply input. When in sleep mode, this supply must be disabled.
Ground	VSS	Common ground Note: The exposed pad must be connected to the ground plane with a via array.