27.5.9 Control C - Host SPI Mode
This register description is valid only when the USART is in Host SPI mode (CMODE written to MSPI). For other CMODE values, see CTRLC - Normal Mode.
See 27.3.3.1.3 USART in Host SPI Mode for a full description of the Host SPI mode operation.
| Name: | CTRLC |
| Offset: | 0x07 |
| Reset: | 0x02 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMODE[1:0] | UDORD | UCPHA | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 1 | |||||
Bits 7:6 – CMODE[1:0] USART Communication Mode
Writing a value different than
0x03 to these bits alters the available bit fields in this
register. See CTRLC - Normal Mode.
| Value | Name | Description |
|---|---|---|
| 0x00 | ASYNCHRONOUS | Asynchronous USART |
| 0x01 | SYNCHRONOUS | Synchronous USART |
| 0x02 | IRCOM | Infrared Communication |
| 0x03 | MSPI | Host SPI |
Bit 2 – UDORD USART Data Order
This bit controls the frame format. The receiver and transmitter use the same setting. Changing the setting of the UDORD bit will corrupt all ongoing communication for both the receiver and the transmitter.
| Value | Description |
|---|---|
| 0 | MSb of the data word is transmitted first |
| 1 | LSb of the data word is transmitted first |
Bit 1 – UCPHA USART Clock Phase
This bit controls the phase of the interface clock. Refer to the 27.3.3.1.3.2 Clock Generation section for more information.
| Value | Description |
|---|---|
| 0 | Data are sampled on the leading (first) edge |
| 1 | Data are sampled on the trailing (last) edge |