24.3.3.1.7 Single-Shot Mode

Use the Single-Shot mode to generate a pulse with a duration defined by the Compare (TCBn.CCMP) register every time a rising or falling edge is observed on a connected event channel.

This mode requires TCB to be configured as an event user and is explained in the Events section.

When the counter stops, the output pin is set low. If an event is detected on the connected event channel, the timer will reset and start counting from BOTTOM to TOP while driving its output high. Read the Status (TCBn.STATUS) register RUN bit to see if the counter is counting. Once the value of CNT reaches the CCMP register, the counter will cease counting. Simultaneously, the output pin will transition to a low state for at least one counterclock cycle (TCB_CLK). During this period, any new event that occurs will be disregarded. Following this, there is a two peripheral clock cycles (PER_CLK) delay before the output is set high after receiving a new event. When the EDGE bit of the TCB.EVCTRL register is written to ‘1’, and any edge can trigger the start of the counter. Only positive edges trigger the start if the EDGE bit is ‘0’.

The counter will start counting as soon as the peripheral is enabled, even without triggering by an event or if the Event Edge (EDGE) bit in the Event Control (TCBn.EVCTRL) register is modified while the peripheral is enabled, which is prevented by writing TOP to the Counter register. A similar behavior is seen if the Event Edge (EDGE) bit in the Event Control (TCBn.EVCTRL) register is ‘1’ while the module is enabled. Writing TOP to the Counter register prevents this as well.

If the Event Asynchronous (ASYNC) bit in the Control B (TCBn.CTRLB) register is written to ‘1’, the timer will react asynchronously to an incoming event. An edge on the event will immediately cause the output signal to be set. The counter will still start counting two complete clock cycles after receiving the event, resulting in an observed delay of two to three clock cycles.