36.3.8.1 Chip Erase

The next steps must be followed to issue a chip erase:
  1. Enter the Chip Erase key by using the KEY instruction. See the Key Activation Signatures table for the CHIPERASE signature.
  2. Enter the NVM Programming key by using the KEY instruction. See the Key Activation Signatures table for the NVMPROG signature. This will prevent a freshly erased device from failing the CRC (if activated).
  3. Read the ASI Key Status (UPDI.ASI_KEY_STATUS) register to verify that both the Chip Erase Key Status (CHER) and the NVM Programming Key Status (NVMPROG) bits are set.
  4. Write the signature to the Reset Request (RSTREQ) bit in the ASI Reset Request (UPDI.ASI_RESET_REQ) register. This will issue a System Reset.
  5. Write 0x00 to the ASI Reset Request (UPDI.ASI_RESET_REQ) register to clear the System Reset.
  6. Read the NVM Lock Status (LOCKSTATUS) bit from the ASI System Status (UPDI.ASI_SYS_STATUS) register.
  7. The chip erase is done when the LOCKSTATUS bit is ‘0’. If the LOCKSTATUS bit is ‘1’, return to step 5.
  8. Check the Chip Erase Key Failed (ERASEFAIL) bit in the ASI System Status (UPDI.ASI_SYS_STATUS) register to verify if the chip erase was successful.
  9. If the ERASEFAIL bit is ‘0’, the chip erase was successful.

After a successful chip erase, the lock bits will be cleared, and the UPDI will have full access to the system. Until the lock bits are cleared, the UPDI cannot access the system bus, and only CS-space operations can be performed.

CAUTION: During chip erase, the BOD is forced in ON state by writing to the Active (ACTIVE) bit field from the Control A (BOD.CTRLA) register and uses the BOD Level (LVL) bit field from the BOD Configuration (FUSE.BODCFG) fuse and the BOD Level (LVL) bit field from the Control B (BOD.CTRLB) register. If the supply voltage VDD is below that threshold level, the device is unavailable until VDD is increased adequately. See the BOD - Brown-out Detector section for more details.