3.4.2 Implementation Example

When routing a 32-bit bus width DRAM interface, it is recommended to use 2x16-bit memory devices. The two devices should be routed using a tree topology, with a midpoint split for the address/command/control signals bus.

For this bus, length matching should be done so that traces connecting the individual memory device to the MPU are matched within a margin.

Traces from each data byte lane should also be matched within its own lane.

It is good practice to route data signals that belong to the same byte lane on the same layer. Figure 3-10 shows the signal routing of data byte lane 0 and 2. For the address/command/control signals bus in Figure 3-9, the routing constraints can be relaxed and routing can be made on any available signal layer.

It is recommended to route the DRAM clock and DQS differential signals on the top and bottom layer, or on the same layer as the rest of the signals from the same group.